Fault-tolerant logical gate networks for Calderbank-Shor-Steane codes
Fault-tolerant logical gate networks for Calderbank-Shor-Steane codes
复制标题
Calderbank-Shor-Steane 码的容错逻辑门网络
DOI：
10.1103/physreva.72.052335
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发表时间：
2003
影响因子：
2.9
通讯作者：
Ben Ibinson
中科院分区：
文献类型：
--
作者：
Andrew M. Steane;Ben Ibinson
讨论了由Calderbank-Shor-Steane码编码的量子比特的容错逻辑运算，重点是适用于高速率编码的方法，每个块编码k个量子比特，k>1。它表明，在一个给定的块内的逻辑量子位可以通过一个单一的恢复操作，在任何状态的稳定器生成器分为X和Z部分。讨论了移动逻辑量子位和实现受控非门和Toffoli门的优化方法。发现当k>1和k=1时，完成容错量子计算所需的时间步数是相同的。
Fault-tolerant logical operations for qubits encoded by Calderbank-Shor-Steane codes are discussed, with emphasis on methods that apply to codes of high rate, encoding k qubits per block with k>1. It is shown that the logical qubits within a given block can be prepared by a single recovery operation in any state whose stabilizer generator separates into X and Z parts. Optimized methods to move logical qubits around and to achieve controlled-NOT and Toffoli gates are discussed. It is found that the number of time steps required to complete a fault-tolerant quantum computation is the same when k>1 as when k=1.
影响因子：
2.9
作者：
Calderbank, AR;Shor, PW
通讯作者：
Shor, PW