Chimera: A Hybrid Machine Learning-Driven Multi-Objective Design Space Exploration Tool for FPGA High-Level Synthesis
Chimera: A Hybrid Machine Learning-Driven Multi-Objective Design Space Exploration Tool for FPGA High-Level Synthesis
复制标题
Chimera：用于 FPGA 高级综合的混合机器学习驱动的多目标设计空间探索工具
DOI：
10.1007/978-3-030-91608-4_52
复制
发表时间：
2022
期刊：
影响因子：
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通讯作者：
Deming Chen
中科院分区：
文献类型：
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作者：
Mang Yu;Sitao Huang;Deming Chen
近年来，基于现场可编程门阵列（FPGA）的硬件加速器已被广泛采用，这要归功于FPGA非凡的可扩展性。然而，随着高度灵活性的到来，设计和优化方面的困难也随之而来。传统上，这些加速器是用低级硬件描述语言设计的，这意味着创建具有复杂行为的大型设计非常困难。因此，创建了高级综合（HLS）工具来简化FPGA的硬件设计。它们使用户能够使用高级语言创建硬件设计，并提供各种优化指令，以帮助提高合成硬件的性能。然而，应用这些优化来实现高性能是耗时的，并且通常需要专业知识。为了解决这个困难，我们提出了一个自动化的设计空间探索工具，用于应用HLS优化指令，称为Chimera，它大大减少了创建高性能HLS设计所需的人力和专业知识。它采用了一种新颖的多目标探索方法，无缝集成了主动学习，进化算法和汤普森采样，使其能够在帕累托曲线上找到一组优化设计，在探索过程中只需评估少量设计点。在实验中，在不到24小时的时间里，这种混合方法探索了与专家HLS用户从Rosetta基准套件创建的高度优化的手动调整设计相比具有相同或上级性能的设计点。除了发现极端点之外，它还探索了帕累托边界，其中手肘点可以潜在地节省高达26%的触发器资源，而延迟可以忽略不计。
—In recent years, hardware accelerators based on field-programmable gate arrays (FPGAs) have been widely adopted, thanks to FPGAs’ extraordinary flexibility. However, with the high flexibility comes the difficulty in design and optimization. Conventionally, these accelerators are designed with low-level hardware descriptive languages, which means creating large designs with complex behavior is extremely difficult. There- fore, high-level synthesis (HLS) tools were created to simplify hardware designs for FPGAs. They enable the user to create hardware designs using high-level languages and provide various optimization directives to help to improve the performance of the synthesized hardware. However, applying these optimizations to achieve high performance is time-consuming and usually requires expert knowledge. To address this difficulty, we present an automated design space exploration tool for applying HLS optimization directives, called Chimera, which significantly reduces the human effort and expertise needed for creating high- performance HLS designs. It utilizes a novel multi-objective exploration method that seamlessly integrates active learning, evolutionary algorithm, and Thompson sampling, making it capable of finding a set of optimized designs on a Pareto curve with only a small number of design points evaluated during the exploration. In the experiments, in less than 24 hours, this hybrid method explored design points that have the same or superior performance compared to highly optimized hand-tuned designs created by expert HLS users from the Rosetta benchmark suite. In addition to discovering the extreme points, it also explores a Pareto frontier, where the elbow point can potentially save up to 26% of Flip-Flop resource with negligibly higher latency.
DOI：
10.1145/3373087.3375306
发表时间：
2020-01
期刊：
Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
影响因子：
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作者：
Pengfei Xu;Xiaofan Zhang;Cong Hao;Yang Zhao;Yongan Zhang;Yue Wang;Chaojian Li;Zetong Guan;Deming Chen;Yingyan Lin
通讯作者：
Pengfei Xu;Xiaofan Zhang;Cong Hao;Yang Zhao;Yongan Zhang;Yue Wang;Chaojian Li;Zetong Guan;Deming Chen;Yingyan Lin