Towards high-performance packet processing on commodity multi-cores: current issues and future directions
Towards high-performance packet processing on commodity multi-cores: current issues and future directions
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迈向商品多核的高性能数据包处理：当前问题和未来方向
DOI：
10.1007/s11432-015-5484-6
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发表时间：
2015-11
期刊：
影响因子：
--
通讯作者：
Zhang Minxuan
中科院分区：
文献类型：
--
作者：
Yan Jinli;Sun Zhigang;Li Tao;Zhang Minxuan
随着电子商务、社交软件、在线视频等新型网络服务的出现，对可编程性的需求越来越迫切。商用多核CPU在网络数据包处理中得到了广泛的应用，以获得高可编程性并缩短上市时间。然而，商品多核的分组处理性能与传统的分组处理硬件（例如，NP（Network Process）。近年来，优化商用多核的数据包处理性能已成为工业界和学术界的热门话题。本文在详细分析数据包处理过程的基础上，首先确定了两个主要的开销，即虚拟到物理地址转换和数据包缓冲区管理。其次，对现有的优化方法进行了综述。第三，在调研的基础上，提出了商用多核+ FPGA的异构体系结构作为提高数据包处理性能的一种有效途径。第四，提出了一种新的自描述缓冲区（SDB）管理技术，以消除分配和释放的数据包缓冲区卸载到FPGA的开销。然后，设计并实现了一个评估测试床PIOT（Packet I/O Testbed），用于评估数据包转发性能。基于PIOT对不同商品多核CPU的I/O容量和优化方法的性能进行了评估和比较。最后，对多核CPU上数据包处理优化的未来工作进行了展望。
The demands of programmability have become more and more exigent as novel network services appear, such as E-commerce, social softwares, and online videos. Commodity multi-core CPUs have been widely applied in network packet processing to get high programmability and reduce the time-to-market. However, there is a great gap between the packet processing performance of commodity multi-core and that of the traditional packet processing hardware, e.g., NP (Network Process). Recently, optimization of the packet processing performance of commodity multi-cores has become a hot topic in industry and academia. In this paper, based on a detailed analysis of the packet processing procedure, firstly we identify two dominating overheads, namely the virtual-to-physical address translation and the packet buffer management. Secondly, we make a comprehensive survey on the current optimization methods. Thirdly, based on the survey, the heterogeneous architecture of the commodity multi-core + FPGA is proposed as a promising way to improve the packet processing performance. Fourthly, a novel Self-Described Buffer (SDB) management technology is introduced to eliminate the overheads of the allocation and deallocation of the packet buffers offloaded to FPGA. Then, an evaluation testbed, named PIOT (Packet I/O Testbed), is designed and implemented to evaluate the packet forwarding performance. I/O capacity of different commodity multi-core CPUs and the performance of optimization methods are assessed and compared based on PIOT. At last, the future work of packet processing optimization on multi-core CPUs is discussed.
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DOI：
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发表时间：
2005-05
期刊：
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影响因子：
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期刊：
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