A heterogeneous SDR MPSoC in 28nmCMOS for low-latency wireless applications

A heterogeneous SDR MPSoC in 28nmCMOS for low-latency wireless applications
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适用于低延迟无线应用的 28nmCMOS 异构 SDR MPSoC

DOI:
10.1145/3061639.3062188
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发表时间:
2017
期刊:
2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC)
影响因子:
--
通讯作者:
J. Uhlig
J. Uhlig
中科院分区:
--
文献类型:
--
作者:
S. Haas;T. Seifert;B. Nöthen;S. Scholze;S. Höppner;A. Dixius;E. Pérez Adeva;T. Augustin;F. Pauls;S. Moriam;M. Hasler;E. Fischer;Y. Chen;E. Matus;G. Ellguth;S. Hartmann;S. Schiefer;L. Cederström;D. Walter;S. Henker;S. Hänzsche;J. Uhlig

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当前和未来的应用对软件定义无线电(SDR)平台在延迟、可靠性和灵活性方面提出了很高的要求。本文提出了一种具有六边形片上网络的异构型SDR MPSoC来解决这些问题。它具有四个数据处理模块和一个用于迭代多输入多输出(MIMO)接收的基带处理引擎。集成的内存控制器支持动态数据流映射和应用程序隔离。在4x4MIMO应用场景中,MPSoC的吞吐量为232Mbit/S,时延为20μS,功耗为414 mW。在吞吐量方面,它的表现比最先进的平台高出4倍。
Current and future applications impose high demands on software-defined radio (SDR) platforms in terms of latency, reliability, and flexibility. This paper presents a heterogeneous SDR MPSoC with a hexagonal network-on-chip to address these issues. It features four data processing modules and a baseband processing engine for iterative multiple-input multiple-output (MIMO) receiving. Integrated memory controllers enable dynamic data flow mapping and application isolation. In a 4 x 4 MIMO application scenario, the MPSoC achieves a throughput of 232 Mbit/s with a latency of 20 μs while consuming 414 mW. It outperforms state-of-the-art platforms in terms of throughput by a factor of 4.
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