Random clock against differential power analysis
Random clock against differential power analysis
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针对差分功耗分析的随机时钟
DOI：
10.1109/apccas.2010.5774887
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发表时间：
2010
期刊：
影响因子：
--
通讯作者：
Boey K
中科院分区：
文献类型：
--
作者：
Boey K
密码系统正受到功率分析攻击的威胁。本文提出了一种新的对抗功率分析攻击的技术，该技术在执行操作时动态改变时钟（使其难以在时域内关联电源走线），并在空闲时钟周期内插入虚拟操作（降低有用信息的信噪比）。通过对基于fpga的电路板上实现的AES加密算法的基本、中间（随机时钟）和高级（随机时钟和虚拟数据）设计进行DPA攻击，证明了其有效性。与基本设计相比，中间设计可抵抗经典DPA攻击，高级设计可将信噪比降低79%（面积增加70%，性能降低5.33%）。结果表明，该设计在这两个指标上都优于其他对抗技术。
Cryptographic systems are being compromised by power analysis attacks. In this paper, a novel countermeasure technique against power analysis attacks is proposed which dynamically varies the clock when executing operations (making it difficult to correlate power traces in the time domain) and inserts dummy operations during idling clock cycles (reducing the signal-to-noise ratio of the useful information). Its effectiveness is shown by performing a DPA attack on basic, intermediate (random clock) and advanced (random clock and dummy data) designs for the AES encryption algorithm, implemented on a FPGA-based board. The intermediate design is resistant to classical DPA attacks and the advanced design reduces the SNR by 79% (increasing area by 70% and reducing performance by 5.33%) when compared to the basic design. It is shown that the design is better in both metrics than other countermeasure techniques.
AES Sbox 设计对功率分析的安全性
DOI：
10.1109/icecs.2010.5724741
发表时间：
2010
期刊：
--
影响因子：
--
作者：
Boey K
通讯作者：
Boey K
用于安全应用的双轨电路的设计和分析
影响因子：
3.7
作者：
D. Sokolov;Julian P. Murphy;A. Bystrov;A. Yakovlev
通讯作者：
A. Yakovlev