High-Level Approaches for Leveraging Deep-Memory Hierarchies on Modern Supercomputers

High-Level Approaches for Leveraging Deep-Memory Hierarchies on Modern Supercomputers
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在现代超级计算机上利用深度内存层次结构的高级方法

DOI:
10.1007/978-981-13-7729-7_9
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发表时间:
2019
期刊:
Singapore
影响因子:
--
通讯作者:
Antonio Gómez-Iglesias, Ritu Arora
Antonio Gómez-Iglesias, Ritu Arora
中科院分区:
--
文献类型:
--
作者:
Antonio Gómez-Iglesias, Ritu Arora

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人们对超级计算机的需求日益增长,这些超级计算机可以支持内存密集型应用程序,以解决来自各个领域的大规模问题。具有快速和复杂的存储器子系统的新型超级计算机正在提供以满足这一需求。虽然复杂和深内存层次结构提供了增加的内存带宽,但它们也会引入额外的延迟。需要优化应用程序的内存使用以提高性能。但是,如果完全手动完成,这可能是一项工作量大且耗时的活动。因此,需要在现代超级计算机上支持存储器管理和存储器优化的高级方法。这种可扩展的方法可以帮助支持开放科学数据中心的用户-主要是领域科学家和学生-进行代码现代化工作。在本文中,我们提出了一个内存管理和优化工作流程的基础上,高层次的工具。虽然工作流程可以推广到具有不同架构的超级计算机,但我们在德克萨斯州高级计算中心的Stampede2系统上演示了其使用情况,该系统包含英特尔Knights Landing和英特尔至强处理器,每个Knights Landing节点都提供DDR4和MCDRAM。
There is a growing demand for supercomputers that can support memory-intensive applications to solve large-scale problems from various domains. Novel supercomputers with fast and complex memory subsystems are being provisioned to meet this demand. While complex and deep-memory hierarchies offer increased memory-bandwidth they can also introduce additional latency. Optimizing the memory usage of the applications is required to improve performance. However, this can be an effort-intensive and a time-consuming activity if done entirely manually. Hence, high-level approaches for supporting the memory-management and memory-optimization on modern supercomputers are needed. Such scalable approaches can contribute towards supporting the users at the open-science data centers - mostly domain scientists and students - in their code modernization efforts. In this paper, we present a memory management and optimization workflow based on high-level tools. While the workflow can be generalized for supercomputers with different architectures, we demonstrate its usage on the Stampede2 system at the Texas Advanced Computing Center that contains both Intel Knights Landing and Intel Xeon processors, and each Knights Landing node offers both DDR4 and MCDRAM.
适用于带宽敏感型 HPC 应用程序的内存异构感知运行时系统
DOI: 10.1109/ipdpsw.2017.168
发表时间: 2017
期刊: 2017 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)
影响因子: --
作者:
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DOI: 10.1007/978-3-319-46079-6_22
发表时间: 2016
期刊: 2017 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)
影响因子: --
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DOI: 10.1145/3093338.3093352
发表时间: 2017
期刊: Success and Impact
影响因子: --
作者:
Arora, Ritu;Koesterke, Lars
通讯作者: Koesterke, Lars
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DOI: 10.1007/s11554-017-0723-2
发表时间: 2017
影响因子: 3
作者:
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DOI: 10.1145/3093338.3093385
发表时间: 2017
期刊: Success and Impact (PEARC17
影响因子: --
作者:
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通讯作者: Panda, D.