Selecting Representative Critical Paths for Sensor Placement Provides Early FPGA Aging Information

Selecting Representative Critical Paths for Sensor Placement Provides Early FPGA Aging Information
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选择传感器放置的代表性关键路径可提供早期 FPGA 老化信息

DOI:
10.1109/tcad.2019.2953174
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发表时间:
2020
影响因子:
2.9
通讯作者:
Z. Navabi
Z. Navabi
中科院分区:
计算机科学3区
文献类型:
--
作者:
Mohammad Ebrahimi;Z. Navabi

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提出了一种用于现场可编程门阵列老化监测的关键路径选择和延迟传感器插入方法。老化信息可用于重新配置现场可编程门阵列以实现更好的性能或磨损均衡。为了不那么积极地过滤老化的路径,我们的方法基于物理层参数[例如路径延迟、进程变化、温度、静态应力(占空比)和动态应力(切换活动)以及与老化相关的参数(例如扇出和端点物理位置)]来决定。在选择了一组最优路径后,我们在前面的工作中引入的年龄传感器以分布式的方式放置在整个FPGA区域中,以提供其各个部件在使用时的老化信息。为了确定上述参数对老化的贡献,需要建立准确的现场可编程门阵列老化模型。在本文中,通过基于测量的拟合方法,将ASIC的老化模型应用于现场可编程门阵列。使用不同基准测试的实验结果表明,我们的算法以最小的误差选择路径。
This article proposes a methodology for critical path selection and delay sensor insertion for aging monitoring in field-programmable gate arrays (FPGAs). The aging information can be used to reconfigure FPGAs to achieve better performance or wear leveling. To filter out the paths aging less aggressively, our methodology decides based on both physical-level parameters [e.g., path delay, process variation, temperature, static stress (duty cycle), and dynamic stress (switching activity) as well as aging-relevant parameters (e.g., fan-out, and endpoint physical location)]. After selection of an optimal set of paths, age sensors, introduced in our earlier work, are placed in a distributed fashion throughout the FPGA area to provide aging information of its various parts as they are being used. Accurate aging models for FPGAs are required to determine the contribution of the above-mentioned parameters in aging. In this article, ASICs’ aging models are adapted for FPGAs through measurement-based fitting approach. The experimental results using various benchmarks reveal that our algorithm selects paths with a minimum error.
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