Sliced integral histogram: an efficient histogram computing algorithm and its FPGA implementation
Sliced integral histogram: an efficient histogram computing algorithm and its FPGA implementation
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切片积分直方图:一种高效的直方图计算算法及其FPGA实现
DOI:
10.1007/s11042-016-3816-1
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发表时间:
2017-06
期刊:
影响因子:
--
通讯作者:
Dong, Qi-Fan
中科院分区:
文献类型:
--
作者:
Yang, Yang;Liu, Yun-Xia;Dong, Qi-Fan
Integral histogram provides efficient histogram computation for all possible target regions, and is widely applied in many computer vision tasks. In this paper, to address the intensive computation and frequent memory accessing bottleneck in real-time applications, a sliced integral histogram algorithm is proposed for efficient integral histogram computation. We explore how maximum parallel computation and storage reduction are simultaneously achieved. Hardware implementation architecture on Field-programmable gate array (FPGA) platform is presented. We also suggest criterion for the optimal number of slices, which allows the most appropriate architecture to be selected. Comparing with the state-of-the-art methods, experimental results on Cyclone platform demonstrate the validity of the proposed algorithm in terms of computation speed, storage capacity and power consumption. Meanwhile, the proposed algorithm can be extended to other histogram based feature descriptors and implemented on any parallel processing platforms.
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