Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse
Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse
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基于中介层的 2.5D 小芯片集成的架构、芯片和封装协同设计流程，实现异构 IP 重用
DOI：
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发表时间：
2020
影响因子：
2.8
通讯作者：
S. Lim
中科院分区：
文献类型：
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作者：
Jinwoo Kim;Gauthaman Murali;Heechun Park;Eric Qin;Hyoukjun Kwon;Venkata Chaitanya Krishna Chekuri;N. Rahman;N. Dasari;Ashutosh Kumar Singh;Minah Lee;H. Torun;Kallol Roy;M. Swaminathan;S. Mukhopadhyay;T. Krishna;S. Lim
系统芯片（SoC）设计的一个新趋势是使用2.5-D集成的基于芯片的IP重用。完整的电子系统可以通过将小芯片集成在插入器上而不是通过单片流程来创建。这种方法扩展了对大量现成知识产权（IP）的访问，允许重用它们，并支持不同技术中的块的异构集成。在本文中，我们提出了一个高度集成的设计流程，包括架构，电路和封装，以构建和模拟异构的2.5-D设计。我们的目标设计是基于精简指令集计算机（RISC）-V处理器的64核架构。我们首先通过添加逻辑协议转换器和物理接口模块来对每个IP进行芯片化。我们将64核处理器的给定寄存器传输级（RTL）转换为小芯片，并通过集中式片上网络进行增强。接下来，我们使用我们的工具来获得物理布局，随后用于合成芯片到芯片I/O驱动器，这些小芯片被放置/路由在硅中介层上。我们的封装模型用于计算2.5维设计的功耗、性能和面积（PPA）以及可靠性。我们的设计空间探索（DSE）研究表明，2.5-D集成产生1.29美元 10万美元，2.19美元 与2-D对应物相比，5倍的面积开销。此外，我们进行DSE研究的电源传输方案和中介层技术，调查在2.5-D集成芯片（IC）设计的权衡。
A new trend in system-on-chip (SoC) design is chiplet-based IP reuse using 2.5-D integration. Complete electronic systems can be created through the integration of chiplets on an interposer, rather than through a monolithic flow. This approach expands access to a large catalog of off-the-shelf intellectual properties (IPs), allows reuse of them, and enables heterogeneous integration of blocks in different technologies. In this article, we present a highly integrated design flow that encompasses architecture, circuit, and package to build and simulate heterogeneous 2.5-D designs. Our target design is 64-core architecture based on Reduced Instruction Set Computer (RISC)-V processor. We first chipletize each IP by adding logical protocol translators and physical interface modules. We convert a given register transfer level (RTL) for 64-core processor into chiplets, which are enhanced with our centralized network-on-chip. Next, we use our tool to obtain physical layouts, which is subsequently used to synthesize chip-to-chip I/O drivers and these chiplets are placed/routed on a silicon interposer. Our package models are used to calculate power, performance, and area (PPA) and reliability of 2.5-D design. Our design space exploration (DSE) study shows that 2.5-D integration incurs $1.29 imes $ power and $2.19 imes $ area overheads compared with 2-D counterpart. Moreover, we perform DSE studies for power delivery scheme and interposer technology to investigate the tradeoffs in 2.5-D integrated chip (IC) designs.
使用标准 ASIC CAD 工具进行 2.5D 系统的小芯片封装协同设计
DOI：
10.1109/asp-dac47756.2020.9045734
发表时间：
2020
期刊：
2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC
影响因子：
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作者：
Kabir, MD Arafat;Peng, Yarui
通讯作者：
Peng, Yarui