The Potential of Programmable Logic in the Middle: Cache Bleaching
The Potential of Programmable Logic in the Middle: Cache Bleaching
复制标题
中间可编程逻辑的潜力：缓存漂白
DOI：
10.1109/rtas48715.2020.00006
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发表时间：
2020
期刊：
影响因子：
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通讯作者：
R. Mancuso
中科院分区：
文献类型：
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作者：
Shahin Roozkhosh;R. Mancuso
将硬实时系统合并到现代多核系统片（SOC）上是一个开放的挑战。硬件资源在内存层次结构上的广泛共享引起了重要的不可预测性问题。由于预计将在下一代网络物理系统（CPS）中使用实时保证来处理更多计算要求的工作负载，因此问题加剧了。大量作品通过提出新颖的硬件重新设计，并提出仅软件解决方案来减轻性能干扰，从而解决了问题。我们概述了一种有希望的新资源管理方法。我们证明，可以在传统的多核处理器和主内存之间引入可编程逻辑内（PLIM）。这提供了操纵单个内存交易的独特功能。我们建议在商业多核SOC上实施PLIM模块的概念验证系统。然后利用PLIM方法来解决高速缓存着色的长期问题。多亏了PLIM，可以在主内存中重新压缩彩色稀疏地址。这是我们称为“高速缓存漂白”技术背后的基本原理。我们在实际应用上评估了我们的设计，并提出了管理程序级适应性，以展示PLIM方法的潜力。
Consolidating hard real-time systems onto modern multi-core Systems-on-Chip (SoC) is an open challenge. The extensive sharing of hardware resources at the memory hierarchy raises important unpredictability concerns. The problem is exacerbated as more computationally demanding workload is expected to be handled with real-time guarantees in next-generation Cyber-Physical Systems (CPS). A large body of works has approached the problem by proposing novel hardware redesigns, and by proposing software-only solutions to mitigate performance interference.Strong from the observation that unpredictability arises from a lack of fine-grained control over the behavior of shared hardware components, we outline a promising new resource management approach. We demonstrate that it is possible to introduce Programmable Logic In-the-Middle (PLIM) between a traditional multi-core processor and main memory. This provides the unique capability of manipulating individual memory transactions. We propose a proof-of-concept system implementation of PLIM modules on a commercial multi-core SoC. The PLIM approach is then leveraged to solve long-standing issues with cache coloring. Thanks to PLIM, colored sparse addresses can be re-compacted in main memory. This is the base principle behind the technique we call Cache Bleaching. We evaluate our design on real applications and propose hypervisor-level adaptations to showcase the potential of the PLIM approach.
DOI：
10.4230/lipics.ecrts.2018.1
发表时间：
2017-07
期刊：
2017 IEEE International Symposium on Workload Characterization (IISWC)
影响因子：
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作者：
F. Farshchi;P. K. Valsan;R. Mancuso;H. Yun
通讯作者：
F. Farshchi;P. K. Valsan;R. Mancuso;H. Yun
在现代异构 MPSoC 平台上设计混合关键应用
DOI：
10.4230/lipics.ecrts.2019.27
发表时间：
2019
期刊：
Euromicro Conference on Real-Time Systems (ECRTS 2019
影响因子：
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作者：
Gracioli, Giovani;Tabish, Rohan;Mancuso, Renato;Mirosanlou, Reza;Pellizzoni, Rodolfo;Caccamo, Marco
通讯作者：
Caccamo, Marco