Presidential Young Investigator Award: Computer Tools for VLSI

总统青年研究员奖：VLSI 计算机工具

• 批准号: 8451822
• 负责人: Mark Horowitz
• 金额: $ 31.2万
• 依托单位: Stanford University
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 1985
• 资助国家: 美国
• 起止时间: 1985-09-01 至 1991-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=8451822&HistoricalAwards=false
• 关键词: Presidential; Young; Investigator; Award; Computer

This research program explores the use of computer tools for VLSI. One problem being studied is expediting the synthesis-verification cycle inherent in computer-aided design. In all large designs, a substantial portion of effort is made implementing and verifying design changes. Although tools are available to aid in checking the design, these tools start the verification from scratch each time they are run. By designing a verification tool that accepts changes to the design interactively, it is possible to reduce the time and cost required to design integrated circuits. In addition to working on methods to improve tool performance, the research is looking at tools to improve chip performance. Using background information in both circuit design and CAD tools, methods are investigated to incorporate design knowledge initially into analysis tools, with the ultimate goal of incorporating these ideas into synthesis tools.

本研究计划探讨使用计算机工具的超大规模集成电路。 一 正在研究的问题是加快综合-验证周期 计算机辅助设计中固有的。 在所有大型设计中， 部分工作是实施和验证设计变更。 尽管有工具可用于帮助检查设计，但这些工具 每次运行时都从头开始验证。 通过 设计接受设计变更的验证工具 交互式地，可以减少 设计集成电路。 除了研究方法， 改善工具性能，研究正在寻找工具，以改善 芯片性能 在电路设计中使用背景信息 和CAD工具，方法进行了研究，以纳入设计知识 最初是分析工具，最终目标是将 将这些想法转化为合成工具。