Presidential Young Investigator Award: Computer Tools for VLSI

这项研究计划探索计算机工具在VLSI中的使用。正在研究的一个问题是加快计算机辅助设计中固有的综合-验证周期。在所有大型设计中，相当一部分的工作都是实现和验证设计更改。虽然可以使用工具来帮助检查设计，但这些工具每次运行时都会从头开始验证。通过设计交互地接受对设计的改变的验证工具，可以减少设计集成电路所需的时间和成本。除了致力于改进工具性能的方法外，这项研究还在寻找提高芯片性能的工具。利用电路设计和CAD工具的背景信息，研究了将设计知识初始地整合到分析工具中的方法，最终目标是将这些想法整合到综合工具中。

This research program explores the use of computer tools for VLSI. One problem being studied is expediting the synthesis-verification cycle inherent in computer-aided design. In all large designs, a substantial portion of effort is made implementing and verifying design changes. Although tools are available to aid in checking the design, these tools start the verification from scratch each time they are run. By designing a verification tool that accepts changes to the design interactively, it is possible to reduce the time and cost required to design integrated circuits. In addition to working on methods to improve tool performance, the research is looking at tools to improve chip performance. Using background information in both circuit design and CAD tools, methods are investigated to incorporate design knowledge initially into analysis tools, with the ultimate goal of incorporating these ideas into synthesis tools.