CCSS: Emulating Mixed-Signal VLSI Systems

提案1509126 PI：Mark Horowitz机构：斯坦福大学项目名称：模拟混合信号超大规模集成电路系统项目目标：为了验证模拟和数字组合的超大规模集成电路芯片，我们创建了在数字逻辑仿真器上运行的模拟组件的功能模型。非技术性技术扩展创造了无处不在的计算环境：我们现在有唱歌卡，计算机控制的汽车，很快所有这些设备都将连接到网络。物联网是当今计算研究中最有前途的领域之一。 然而，如果我们要充分实现全连接世界的承诺，就必须解决一个根本问题：如何验证作为这场革命基础的复杂混合信号集成电路。 由于这些芯片紧密耦合模拟和数字模块，我们需要一起验证整个模拟/数字系统。 解决混合信号验证问题是实现这一新未来必须解决的关键挑战，也是本研究的主题。技术：最近的工作已经开始解决这个问题，通过创建可以在数字验证环境中运行的模拟模块模型。这项研究从两个方面扩展了这项先前的工作。首先，它将解决当前模拟建模工作的一些局限性，使其更通用（处理真实的电路中发生的更多类型的情况），并将创建这些模型的过程编入法典。 第一个扩展将使当前的建模技术更容易使用。不幸的是，芯片系统是如此复杂的今天，基于软件的仿真往往是太慢的系统验证。 因此，大多数公司依赖于硬件仿真平台进行验证。因此，我们的第二个目标是进一步扩展我们的模拟功能建模，通过创建一个系统，可以将这些功能模型映射到目前用于硬件仿真的平台上。 这些仿真平台由现场可编程逻辑阵列（FPGA）或定制的仿真芯片组成，我们将探讨两种模拟功能映射的方法：直接将所有模拟模块映射到FPGA逻辑，以及构建模拟模型解释器，并选择最具成本效益的方法。 由于直接映射方法可以保持用于模拟和数字块的时钟速率之间的固定比率，因此构建简单的过采样模拟模型可能是有意义的。这里的挑战是将所需的计算映射到FPGA。 大多数模拟功能可以映射到数字模块，通过查找表（LUT）和滤波器/DSP模块实现。 在解释器方法中，我们将探索构建一个模拟模型评估引擎，当模型的输入发生变化时，该引擎将模拟模型。 如果模拟信号的变化比主FPGA时钟慢，则每个模型评估可能需要许多周期，这是一种更有效的方法。 此外，我们可以构建比模拟功能模型少得多的模型评估引擎。

Proposal 1509126PI: Mark HorowitzInstitution: Stanford UniversityTitle: Emulating Mixed-Signal VLSI SystemsProject Goals:To validate combined analog and digital VLSI chips, we create functional models of the analog components which run on digital logic emulators.Nontechnical Technology scaling created an environment of ubiquitous computing: we now have singing cards, and computer controlled cars, and soon all these devices will be connected to the net. The Internet of Things is one of the most promising areas in computing research today. Yet there is a fundamental problem that must be addressed if we are going to fully realize the promise of a fully connected world: how to validate the complex mixed-signal integrated circuits that are the foundation of this revolution. Since these chips tightly couple analog and digital blocks, we need to validate the entire analog/digital system together. Attacking the mixed-signal validation issue is a key challenge that must be addressed to enable this new future, and it is the topic of this research.Technical:Recent work has started to address this issue, by creating models of the analog blocks that can be run in a digital validation environment. This research extends this prior work in two way. First it will address some of the limitations of the current analog modeling work to both make it more general (handle more types of situations that occur in real circuits), and codify the procedure for creating these models. This first extension will make it much easier to use the current modeling technique. Unfortunately chip systems are so complex today that software based simulation is often too slow for system validation. As a result most companies rely on hardware emulation platforms for validation. Thus our second goal is to further extend our analog function modeling by creating a system that can map these functional models onto a platform currently used for hardware emulation. These emulation platforms either consist of field programmable logic arrays (FPGAs) or custom built emulation chips.We will explore two approaches to analog functional mapping directly mapping all analog blocks to FPGA logic, and building an analog model interpreter and choose the most cost effective approach. Since the direct mapped approach can maintain a fixed ratio between the rates of the clocks used for the analog and digital blocks, it might make sense to build simple oversampled analog models. Here the challenge is in mapping the required computation to the FPGA. Most analog functions can be mapped to digital blocks, implemented with lookup tables (LUTs) and filter/DSP blocks. In the interpreter approach, we will explore building an analog model evaluation engine that will emulate a model when its inputs change. If the analog signals change more slowly than the main FPGA clock, we might have many cycles for each model evaluation, making this a more efficient approach. In addition, it is possible that we can build many fewer model evaluation engines than analog functional models.