A Systematic Methodology for Designing VLSI Systolic Arrays with Applications in Pattern Recognition and Image Processing

点击翻译按钮获取中文摘要

The research is an engineering approach to the solution of two fundamental problems in designing systolic arrays, namely, restructuring of algorithms for increased parallelism and efficient mapping of algorithms into systolic arrays. Two major limitations in the state-of-the-art of existing transformation systems are the nonexistence of powerful systematic semantic transformations and the inability to systematically achieve optimality in the resulting designs. Efforts are underway to investigate: new syntactic and semantic transformations on complex algorithms for optimizing area, time, input/output and other parameters in the systolic architecture; efficient methodology for mapping algorithms onto two- or three-dimensional systolic arrays with feedbacks, replicated data, general timing and limited or full broadcasting and other architectural constraints; design of macropipelines of systolic arrays and the related problems in interconnection, buffering, timing, and closure property; and design of macropipelines of systolic arrays for image processing and pattern recognition. Emphasis is on both theoretical and practical approaches in this research. With the theory developed, an automated design tool will be implemented so that it can be interfaced with existing VLSI design tools.