Reliable VLSI Systems for Digital Signal Processing

在本提案中，数论技术被认为提供硬件模块化，促进VLSI设计中的高数据速率，可测试性，可靠性和容错性。提出了一项研究计划，将解决集成电路和更高系统级别的可靠性和容错问题。本文将研究用于合成孔径雷达（SAR）图像处理的卷积反投影（CBP）数字处理器的模块化设计，以解决电路级和系统级容错问题，并研究电路级错误检查和系统级容错机制之间的相互作用。

In this proposal, number-theoretic techniques are considered to provide hardware modularity that facilitates high data rates, testability, reliability and fault tolerance in VLSI design. A research program is proposed that will address questions of reliability and fault tolerance on both the integrated circuit and the higher system level. Modular designs of a convolutional back-projection (CBP) digital processor for synthetic aperture radar (SAR) image processing will be studied as vehicles to address both circuit and system level fault tolerance, and to study the interaction between circuit level error checking and system level fault tolerance mechanisms.