Performance Evaluation of Parallel Logic Programming Paradigms (Computer and Information Science)

并行逻辑编程范式的性能评估（计算机与信息科学）

• 批准号: 8704576
• 负责人: Michael Flynn
• 金额: $ 7.59万
• 依托单位: Stanford University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 1987
• 资助国家: 美国
• 起止时间: 1987-08-01 至 1989-01-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=8704576&HistoricalAwards=false
• 关键词: Performance; Evaluation; Parallel; Logic; Programming

A shared memory multiprocessor testbed will be built for measuring parallel logic programming language architectures. The purpose of developing the testbed is to compare several parallel implementations of logic programming languages to determine which paradigm offers greater cost-effective performance. An equally important goal is the determination of the memory characteristics of, and memory designs suitable for those languages. The testbed, enabling empirical measurement of benchmark performance, will be composed of architecture emulators and memory simulators running on a host multiprocessor. Processor performance is estimated as required shared memory bandwidth because high speed processors are ultimately limited by memory bandwidth and architectures that require less bandwidth have greater potential for high performance. Memory performance statistics to be collected include local cache miss ratio, traffic ratio, broadcast traffic (necessary to retain consistency between caches). This methodology is most suited for ongoing processor design efforts, like the PIM project at ICOT, because experimental memory designs can be quickly described, tested and results compared with other models. This project is a collaborative effort with the Japanese Institute for New Generation Computer Technology (ICOT) and funded under the NSF/ICOT Visitors Program.

一个共享内存的多处理器测试床将建成 测量并行逻辑编程语言体系结构。 的 开发试验台的目的是比较几种并行 逻辑编程语言的实现，以确定 paradigm提供了更高的成本效益性能。 一个同样 一个重要的目标是确定记忆特性 和适合这些语言的内存设计。 测试平台，能够对基准进行经验性测量 性能，将由体系结构仿真器和 在主机多处理器上运行的内存模拟器。 处理器 性能根据所需的共享内存带宽进行估计 因为高速处理器最终受到存储器的限制 带宽和需要更少带宽的架构 更大的高性能潜力。 内存性能 要收集的统计数据包括本地高速缓存未命中率， 流量比率、广播流量（保持一致性所必需的 缓存之间）。 这种方法最适合于进行 处理器设计工作，如ICOT的PIM项目，因为 实验性的存储器设计可以被快速地描述、测试和 结果与其他模型比较。 这个项目是与日本合作的成果 新一代计算机技术研究所（ICOT） 由NSF/ICOT Visitors Program资助。