Systolic Array Architectures for String Comparisons

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The focus of this research is on the study of systolic architectures for performing high-speed string comparisons. Different systolic array- based architectures are being developed, analyzed, and compared with respect to this class of applications. Detailed architectural descriptions of the most promising array designs are being developed both at the chip level and at the printed circuit-board levels. It is expected that a prototype of the most promising design will be implemented as well as the software needed to support the design. This prototype will be used to evaluate its effectiveness for this class of applications. Results of this research can have a broad impact in a number of areas including speech recognition, spelling correction, compiler error processing, and database retrieval.