Implementation of Maximum Likelihood Decoding for Trellis Codes and Trellis Coded Modulation

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A single chip implementation of a maximum likelihood Viterbi decoder is being studied for use with convolutional codes and trellis coded modulation. The actual final design and fabrication will occur in Phase III. The decoder is matched to all codes with up to 64 states with the property that branches connect any state in the trellis to at most 4 new states. This decoder chip will have extensive applications in digital communication systems and in digital recording systems including magnetic, magneto-optic and optical systems. This chip is expected to be of use in high-speed telephone-line modems, satellite communication, and magnetic recording applications. The maximum-likelihood decoder will significantly reduce the incidence of channel induced errors in the information bit stream, which was previously convolutionally encoded. While the convolutional encoder is easy to implement, the dynamic programming algorithm which constitutes the Viterbi decoder is much more difficult and is thus a very significant contribution.