Research Initiation: Development of Testing and Simulation Methodologies for Infant Failure and Field-Yield Estimationfor MOS VLSI/ULSI Circuits
Research Initiation: Development of Testing and Simulation Methodologies for Infant Failure and Field-Yield Estimationfor MOS VLSI/ULSI Circuits
研究启动：开发 MOS VLSI/ULSI 电路初期故障和现场产量估计的测试和仿真方法
批准号：
8808900
负责人：
Bharat Bhuva
金额：
$6.0万
依托单位：
依托单位国家：
美国
项目类别：
Standard Grant
财政年份：
1988
资助国家：
美国
项目状态：
已结题
起止时间：
1988-08-01 至 1991-01-31
中文摘要
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英文摘要
New switch-level approaches for fast and efficient simulation of MOS IC's are to be formulated in order to estimate "infant" (i.e., early) failures and to estimate field yield in large chips. The simulation scheme is also expected to identify the critical sub-section of circuits that cause early failures and should help in redesigning for greater robustness.
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会议论文
Planning Grant: I/UCRC for Integrated Design-for-Reliability for Electronics
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批准号：1160870
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项目类别：Standard Grant
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资助金额：$1.15万
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财政年份：2012
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负责人：Bharat Bhuva
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依托单位：
海外基金
