A Simple and Reasonably Accurate Characterization on the RC Delay Model of Mosfet for Digital Timing Analysis of CMOSCircuits

本研究涉及应用线性RC建模技术， 对CMOS电路中的时间延迟进行经验建模。 一种工具， 自动表征有效电阻和电容 该系统是为开关级时序模拟器而设计的 或基于线性RC延迟模型的分析仪。 重点是评估 以及改进模型中的精度限制，即： 非线性MOSFET特性的电阻近似;单 多极网络函数的时间常数近似;以及 阶跃输入波形近似。 技术包括：利用 传输门中的非线性体效应，以改善线性 电阻近似;使用简单的单时间常数模型， 使用更精确的双时间常数模型的选项;以及使用 输入上升/下降时间效应的分段线性表征。

This research concerns applying the linear RC modeling technique to model empirically timing delays in CMOS circuits. A tool, which automatically characterizes effective resistances and capacitances of MOSFETSs, is being designed for use in switch level timing simulators or analyzers based on linear RC delay models. Focus is on assessment and improvement of accuracy limitations in the model, namely: linear resistance approximation of the nonlinear MOSFET characteristic; single time constant approximation of the multiple pole network function; and step input waveform approximation. Techniques include: exploiting nonlinear body effect in the transmission gate to improve linear resistance approximation; using a simple single time constant model with an option for using a more accurate two time constant model; and using a piecewise linear characterization of the input rise/fall time effect.