RIA: Synthesis and Implementation of Multi-Rate Arrays

RIA：多速率阵列的综合和实现

• 批准号: 9011227
• 负责人: Sayfe Kiaei
• 金额: $ 6.2万
• 依托单位: Oregon State University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 1990
• 资助国家: 美国
• 起止时间: 1990-06-15 至 1994-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9011227&HistoricalAwards=false
• 关键词: RIA; Synthesis; Implementation; Multi; Rate

The growing demand for high speed real-time signal and image processing has led to many new parallel architectures. Among these systolic arrays is an important class of parallel architectures that has played a significant role in the VLSI implementation of algorithms of these applications. Since systolic arrays are algorithmic specific, it is essential to develop methods for the synthesis and automatic mapping of algorithms onto these arrays. Work by other researchers has addressed the synthesis problem based on uniform recurrence equations (URE) or equivalent specifications of algorithms. Local communication is an essential factor for effective realization of systolic arrays. However, compared to global communication it requires extra delays which reduce the computation time. Particularly, for many fine-grain operations where the PE has a simple structure the additional delay for the transmission of data becomes restrictive. Furthermore, many algorithms can not be directly transformed to UREs or may not exhibit the property of locality. The locality restriction can be solved by using Multi-Rate Arrays (MRA). These arrays transmit the data in a multi-rate fashion and can be used for many DSP and matrix computations resulting in speed up over systolic arrays. In this project we extend previous design methods for systolic arrays to MRAs in several directions. First, we further develop our recent results on the synthesis of MRAs and obtain a formal procedure for the design automation of MRAs. Secondly, we investigate the application of MRAs to DSP and image processing algorithms. This includes a thorough comparison of MRAs with local broadcast (systolic,) bounded-broadcast, and global broadcast arrays in terms of speedup, efficiency, architecture complexity, number of data paths, and VLSI chip area.

对高速实时信号和图像处理的需求不断增长 导致了许多新的并行架构。 在这些脉动阵列中， 是一类重要的并行架构， 在这些算法的VLSI实现中的重要作用 应用. 由于脉动阵列是算法特定的，因此它是 对于开发合成和自动映射的方法至关重要 算法到这些数组上。 其他研究人员的工作已经解决了 基于均匀递归方程（URE）的综合问题，或 算法的等价规范。 地方交流是有效实现 脉动阵列 然而，与全球通信相比， 减少计算时间的额外延迟。 特别是，对于许多 细粒度操作，其中PE具有简单的结构， 数据传输的延迟变得受限。 此外，委员会认为， 许多算法不能直接转换为URES，或者可能不 表现出局部性。 位置限制可以是 多速率阵列（Multi-Rate Arrays，MRA） 这些阵列传输数据 并可用于许多DSP和矩阵 计算导致速度超过脉动阵列。 在这个项目中，我们扩展了以前的脉动阵列设计方法 向多个方向进行MRA。 首先，我们进一步发展我们最近的 结果的合成MRA，并获得一个正式的程序， MRA的设计自动化。 其次，我们研究了 MRA到DSP和图像处理算法。 这包括一个彻底的 MRA与本地广播（收缩）、有界广播的比较， 和全局广播阵列在加速、效率 架构复杂度、数据路径数量和VLSI芯片面积。