An Equivalent Circuit Model to Analyze Single-Event Upset in CMOS SRAMs

互补金属氧化物硅（CMOS）静态随机存取 存储器（SRAM）单元的尺寸减小了两倍多 随着每一代新SRAM阵列的推出， 现在 过量载流子产生对电路的瞬态效应 为了设计SRAM， 细胞 本研究旨在设计一个等效电路模型 近似于单元瞬态响应的SRAM单元 在一个单一的事件心烦意乱。 该模型将被验证， 数字和实验。 应用于设计 SRAM阵列将被研究。

Complimentary metal oxide silicon (CMOS) static random access memory (SRAM) cells have decreased in size more than two times with the introduction of each new generation of SRAM array. Now the transient effects of excess carrier generation on the circuits of the memory cell must be understood in order to design the SRAM cells. The research is to design an equivalent circuit model of an SRAM cell which approximates the cell transient response during a single event upset. The model will be verified both numerically and experimentally. Applications to the design of SRAM arrays will be investigated.