CISE Research Instrumentation

购置一台100 MHz测试仪将有助于进行测试工作， 验证超大规模集成电路芯片和多芯片配置在一个真实的 环境 在低速下测试芯片不会给出 物理特性（沿传输沿着的反弹和回波 线路、信号干扰等）发生在运行速度下。 该测试仪将使实验能够在芯片设计上完成 为了帮助寻找正确芯片操作的设计规则， 更高的时钟频率 该测试仪还将启用常规测试 的电路来放大。 新的芯片设计以如此高的时钟速率运行， 传统的观点认为，芯片是离散逻辑的集合 元素不再是真的。 相反，芯片被视为 具有开关和信号的传输线集合 调制发生在有源元件点。 为了研究 这种现象，并得出正确的设计规则 在电路测试中，有必要在高时钟频率下测试电路 率 100MHz测试仪将提供该功能。

The acquisition of a 100MHz tester will allow work on testing and validating VLSI chips and multi-chip configurations in a real environment. Testing chips at slow speeds does not give the physical characteristics (bounces and echoes along transmission lines, signal interference etc.) that occur at operating speed. This tester will enable experimentation to be done on chip designs to aid in the search for design rules for correct chip operation at high clock rates. The tester will also enable conventional testing of circuits to be scaled up. New chip designs run at such a high clock rate that the conventional view of the chip as a collection of discrete logic elements no longer holds true. Instead, the chip is viewed as a collection of transmission lines with switching and signal modulation occurring at active element points. In order to study this phenomenon and to derive design rules for the correct design of circuits, it is necessary to test the circuits at a high clock rate. The 100MHz tester will provide that capability.