CISE Research Instrumentation

CISE 研究仪器

• 批准号: 9022505
• 负责人: Patrick Mantey
• 金额: $ 11.04万
• 依托单位: University of California-Santa Cruz
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 1991
• 资助国家: 美国
• 起止时间: 1991-04-01 至 1992-03-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9022505&HistoricalAwards=false
• 关键词: CISE; Research; Instrumentation

The acquisition of a 100MHz tester will allow work on testing and validating VLSI chips and multi-chip configurations in a real environment. Testing chips at slow speeds does not give the physical characteristics (bounces and echoes along transmission lines, signal interference etc.) that occur at operating speed. This tester will enable experimentation to be done on chip designs to aid in the search for design rules for correct chip operation at high clock rates. The tester will also enable conventional testing of circuits to be scaled up. New chip designs run at such a high clock rate that the conventional view of the chip as a collection of discrete logic elements no longer holds true. Instead, the chip is viewed as a collection of transmission lines with switching and signal modulation occurring at active element points. In order to study this phenomenon and to derive design rules for the correct design of circuits, it is necessary to test the circuits at a high clock rate. The 100MHz tester will provide that capability.

100MHz测试仪的采购将允许在真实环境中测试和验证VLSI芯片和多芯片配置。在低速下测试芯片不会给出在运行速度下发生的物理特性（沿着传输线的反弹和回声，信号干扰等）。这个测试器可以在芯片设计上进行实验，以帮助寻找在高时钟速率下正确芯片操作的设计规则。该测试仪还将使传统的电路测试规模扩大。新的芯片设计以如此高的时钟速率运行，以至于将芯片视为离散逻辑元件集合的传统观点不再成立。相反，芯片被看作是在有源元件点具有开关和信号调制的传输线的集合。为了研究这一现象，得出正确设计电路的设计规律，有必要在高时钟速率下对电路进行测试。100MHz测试仪将提供这种能力。