A Bit-Parallel, Word-Parallel, Massively Parallel Associative Processor for Scientific Computing

经典的SIMD关联处理器以位串行字并行的方式执行算术。当前的大规模并行计算机也可以在细粒度计算环境中执行位串行运算。这种位串行特性是提高处理速度的限制因素。在经典关联处理器模型的基础上，提出了一种简单而功能强大的新架构。通过在存储单元切片之间分配逻辑，使多个位平面共享一个简单的逻辑单元，在大规模并行环境中实现位并行运算变得可行。对于m位操作数，像乘法这样的复杂操作在O(m)个周期内执行，而对于位串行机器来说是O（m2）个周期。该架构的简单性使其能够使用VLSI技术实现，从而允许构建字并行，位并行，大规模并行（P3）计算系统。这项工作的主要目标是建立一个实验P3机器，它将被嵌入到一个异构的超级计算环境中。对这种架构和实际工作原型的需求源于许多传统超级计算机无法解决的应用。在这项提案中，空间科学应用被概述，因为这项工作也得到了美国宇航局的支持。

Classical SIMD associative processors execute arithmetic in a bit- serial word-parallel manner. Current massively parallel machines also perform bit-serial arithmetic in a fine grain computing environment. This bit-serial property is a limiting factor in increasing processing speeds. A simple but powerful new architecture based on the classical associative processor model is proposed here. By distributing logic among slices of storage cells such that a number of bit-planes share a simple logic unit, bit- parallel arithmetic in a massively parallel environment becomes feasible. For m-bit operands, complex operations such as multiplications execute in O(m) cycle as opposed to O(m2) for bit- serial machines. The simplicity of the architecture enables its implementation using VLSI technology, and hence allows the construction of a word-Parallel, bit-Parallel, massively Parallel (P3) computing system. The main goal of the proposed work is to build an experimental P3 machine which is to be embedded into a heterogeneous supercomputing environment. The need for such architecture and for an actual working prototype stems from a number of applications which cannot be solved in conventional spercomputers. In this proposal, space science applications are outlined as this work is also supported by NASA.