RIA: Designing VLSI Arithmetic Arrays to Satisfy Precision Constraints

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Digital signal processing (DSP) structures introduce arithmetic error due to finite wordlength effects. Different number representations and arithmetic methods have their associated precision. This research provides a unifying framework within which many different design alternatives can be compared. It studies various VLSI architectures which satisfy constraints on arithmetic precision while maximizing performance and minimizing VLSI system cost. It uses a statistical state-space model to evaluate the precision of fixed-point, floating -point, signed- digital, residue, logarithmic and rational number systems and distributed and CORDIC arithmetics. Unlike conventional microprocessors, dedicated systems can have a multitude of distinct internal wordlengths. The choice of an adequate wordlength can be defined as an integer optimization problem in which arithmetic precision is a constraint and some measures of system cost such as VLSI area (A), latency (L), or period (P), as the objective function. CAD tool will be built to explore the large design space of alternate arithmetic, architectures and wordlengths.