Adaptive Systems-on-a-Chip for Low-Power Signal Processing

用于低功耗信号处理的自适应片上系统

• 批准号: 9988238
• 负责人: Wayne Burleson
• 金额: $ 32.49万
• 依托单位: University of Massachusetts Amherst
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2000
• 资助国家: 美国
• 起止时间: 2000-07-15 至 2004-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9988238&HistoricalAwards=false
• 关键词: Adaptive; Systems; Chip; Low; Power

Future signal processing systems will use a heterogeneous System-on-a-Chip architecture for performance, flexibility, cost and power efficiency. Components will include programmable DSP and RISC cores, memories, dedicated hardware blocks and embedded field programmable logic cores for flexible and late-bound functionality. Adaptation of the system will be required to track time-varying aspects of the environment. Dynamic reconfigurability can be used to adapt algorithms and architectures to time-varying computations in signal processing applications, thus dramatically reducing average power consumption. The objective of this project is to develop theory, methodology, tools, and demonstration of several adaptive signal processing systems using parameterized macros which can be dynamically configured to adapt to the computation and save power. Improvements to embedded field programmable architectures and circuits will be developed to make them better suited for low-power signal processing applications. This includes hardware and software mechanisms at the chip and system level to support the dynamic reconfiguration of parameterized macros to save power. CAD techniques will leverage recent work in incremental place-and-route, macro-based floorplanning, and statically scheduled communication. New design methods and tools will be evaluated in four realistic and complex DSP systems which all have time-varying computations and tight power budgets: 1) an MPEG2 encoder, 2) an FFT-based wireless receiver, 3) a radar for unmanned aircraft, and 4) a wireless LAN prototype. Collaboration with ENST/Paris is anticipated.

未来的信号处理系统将使用异构的片上系统架构，以提高性能、灵活性、成本和功率效率。 组件将包括可编程DSP和RISC核心、存储器、专用硬件模块和嵌入式现场可编程逻辑核心，以实现灵活和后期功能。 将需要对该系统进行调整，以跟踪环境随时间变化的方面。 动态可重构性可用于使算法和架构适应信号处理应用中的时变计算，从而显著降低平均功耗。 这个项目的目标是开发理论，方法，工具和演示的几个自适应信号处理系统，使用参数化的宏，可以动态配置，以适应计算和节省电力。 嵌入式现场可编程架构和电路的改进将被开发，使其更适合低功耗信号处理应用。 这包括芯片和系统级的硬件和软件机制，以支持参数化宏的动态重新配置以节省功率。 CAD技术将利用最近在增量布局布线、基于宏的布局规划和静态调度通信方面的工作。 新的设计方法和工具将在四个现实和复杂的DSP系统中进行评估，这些系统都具有时变计算和严格的功率预算：1）MPEG 2编码器，2）基于FFT的无线接收器，3）无人驾驶飞机的雷达，以及4）无线LAN原型。 预计将与ENST/巴黎合作。