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Adaptive Systems-on-a-Chip for Low-Power Signal Processing

Adaptive Systems-on-a-Chip for Low-Power Signal Processing
用于低功耗信号处理的自适应片上系统
批准号:
9988238
负责人:
Wayne Burleson
金额:
$32.49万
依托单位国家:
美国
项目类别:
Continuing Grant
财政年份:
2000
资助国家:
美国
项目状态:
已结题
起止时间:
2000-07-15 至 2004-06-30

项目摘要

项目成果

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中文摘要
翻译
未来的信号处理系统将采用异构的片上系统架构,以提高性能、灵活性、成本和功率效率。组件将包括可编程DSP和RISC内核、存储器、专用硬件块和嵌入式现场可编程逻辑内核,以实现灵活和后期功能。将需要对系统进行调整,以跟踪环境中随时间变化的方面。动态可重构性可用于使算法和架构适应信号处理应用中的时变计算,从而显着降低平均功耗。这个项目的目标是发展理论、方法、工具,并演示几个使用参数化宏的自适应信号处理系统,这些宏可以动态配置以适应计算并节省电力。将改进嵌入式现场可编程架构和电路,使其更适合低功耗信号处理应用。这包括芯片和系统级的硬件和软件机制,以支持参数化宏的动态重新配置以节省电力。CAD技术将利用最近在增量位置和路线、基于宏的平面规划和静态调度通信方面的工作。新的设计方法和工具将在四个现实和复杂的DSP系统中进行评估,这些系统都具有时变计算和紧张的功率预算:1)MPEG2编码器,2)基于fft的无线接收器,3)无人机雷达,以及4)无线局域网原型。预计将与ENST/Paris合作。
英文摘要
Future signal processing systems will use a heterogeneous System-on-a-Chip architecture for performance, flexibility, cost and power efficiency. Components will include programmable DSP and RISC cores, memories, dedicated hardware blocks and embedded field programmable logic cores for flexible and late-bound functionality. Adaptation of the system will be required to track time-varying aspects of the environment. Dynamic reconfigurability can be used to adapt algorithms and architectures to time-varying computations in signal processing applications, thus dramatically reducing average power consumption. The objective of this project is to develop theory, methodology, tools, and demonstration of several adaptive signal processing systems using parameterized macros which can be dynamically configured to adapt to the computation and save power. Improvements to embedded field programmable architectures and circuits will be developed to make them better suited for low-power signal processing applications. This includes hardware and software mechanisms at the chip and system level to support the dynamic reconfiguration of parameterized macros to save power. CAD techniques will leverage recent work in incremental place-and-route, macro-based floorplanning, and statically scheduled communication. New design methods and tools will be evaluated in four realistic and complex DSP systems which all have time-varying computations and tight power budgets: 1) an MPEG2 encoder, 2) an FFT-based wireless receiver, 3) a radar for unmanned aircraft, and 4) a wireless LAN prototype. Collaboration with ENST/Paris is anticipated.
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