RIA: Asynchronous Computer Architecture

计算机体系结构正在成为一门广为人知的科学。然而，它目前被架构思想的传统同步实现所主导。随着构建异步电路的技术，特别是自定时电路的改进，人们更有理由问这些电路技术可能会对计算机的体系结构产生什么影响。例如，时钟同步电路倾向于反映最坏情况下的行为，因为时钟周期对于通过系统某些组件的最坏情况下的路径必须足够长。另一方面，异步系统倾向于反映平均情况下的性能，因为一个组件的结果在计算完成时可用。异步系统还可以直接利用递增的流程或技术改进，因此可以在更长的时间段内保持生产力。本研究研究了在体系结构级别使用异步来提高性能的方法。开发了一个框架，允许考虑不同的处理器组织。这项研究的结果提出了使用异步来提高处理器性能的体系结构。通过使用自动翻译系统从程序描述生成电路来测试所提出的体系结构的部分。

Computer architecture is becoming a well-understood science. However, it is currently dominated by traditional synchronous implementations of architectural ideas. As techniques for building asynchronous circuits, and self-timed circuits in particular, improve, it becomes more reasonable to ask what effect these circuit techniques might have on the architecture of computers. Clocked synchronous circuits, for example, tend to reflect worst- case behavior because the clock cycle must be long enough for the worst-case path through some component of the system. Asynchronous systems, on the other hand, tend to reflect average-case performance because results from one component are available as the computation completes. Asynchronous systems can also take direct advantage of incremental process or technology improvements and can thus remain productive over longer periods of time. This research studies the ways in which asynchrony can be used to increase performance at an architectural level. A framework is developed that allows different processor organizations to be considered. The result of this study proposed architecture that uses asynchrony to improve processor performance. Parts of the proposed architecture are tested by using an automatic translation system to generate circuits from program descriptions.