Integrating Asynchronous Digital Design and Testing into the Undergraduate Computer Engineering Curriculum

将异步数字设计和测试融入本科计算机工程课程

• 批准号: 0536343
• 负责人: Scott Smith
• 金额: $ 9.48万
• 依托单位: Missouri University of Science and Technology
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2006
• 资助国家: 美国
• 起止时间: 2006-02-15 至 2007-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0536343&HistoricalAwards=false
• 关键词: Integrating; Asynchronous; Digital; Design; Testing

Engineering - Computer (32)This project is improving educational practices and student learning through development of materials that provide for easy integration of asynchronous concepts into existing digital systems course structures. Since demands to increase circuit robustness, decrease power consumption, and alleviate many clock-related issues are starting to cause a shift from synchronous to asynchronous design styles, introducing this material into the computer engineering curriculum is becoming extremely important. The project is developing lecture notes, example problems, group projects, VHDL libraries of fundamental asynchronous components, and various models of fundamental asynchronous components. It is integrating these materials into two undergraduate/graduate-level courses: one on digital system modeling with VHDL and one on VLSI design. The results of this project are being disseminated through appropriate conference presentations and journal publications and the material is available on the web and on a CD-ROM and this availability is being advertised through a microelectronic systems newsletter. Specially designed non-credit tests and quizzes matched to the learning objectives are being used to evaluate student learning, and standard institutional questionnaires are being used to characterize the students' attitudes about the material. A colleague at another institution is conducting a formal review of the material as an external content expert. The broader impacts of the project are resulting from the dissemination of the materials through various publications and postings.

工程-计算机（32）本项目通过开发能够将异步概念轻松集成到现有数字系统课程结构中的材料，改善教育实践和学生学习。由于提高电路健壮性、降低功耗和减轻许多时钟相关问题的需求开始导致从同步设计风格到异步设计风格的转变，因此将这些材料引入计算机工程课程变得极其重要。该项目正在开发课堂讲稿、示例问题、小组项目、基本异步组件的VHDL库以及基本异步组件的各种模型。它将这些材料整合到两个本科/研究生水平的课程中：一个是关于VHDL的数字系统建模，另一个是关于VLSI设计。该项目的成果正通过适当的会议发言和期刊出版物加以传播，材料可在网络和CD-ROM上获得，并正在通过微电子系统通讯进行宣传。正在使用与学习目标相匹配的专门设计的非学分测试和测验来评估学生的学习，并使用标准的机构调查问卷来描述学生对材料的态度。另一个机构的同事正在作为外部内容专家对材料进行正式审查。该项目的更广泛影响是通过各种出版物和帖子传播这些材料。