Research in Computer-Aided Design of VLSI Circuits

超大规模集成电路计算机辅助设计研究

• 批准号: 9222408
• 负责人: C. Liu
• 金额: $ 25.6万
• 依托单位: University of Illinois at Urbana-Champaign
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 1993
• 资助国家: 美国
• 起止时间: 1993-05-01 至 1997-10-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9222408&HistoricalAwards=false
• 关键词: Research; Computer; Aided; Design; VLSI

Liu The research is on algorithms for high level synthesis and layout of VLSI CAD designs. Algorithms for complex, large industrial type design problems are being developed. Research topics include: 1. high level synthesis with testability as an important goodness measure, 2. timing driven placement algorithms for EPGAs, and 3. channel and switchbox routing in which the effect of cross talk is to be taken into consideration. For the first problem, the effect of register allocation and functional unit binding on the testability of the circuit is being examined. Then the scheduling step is being examined. Research on the second problem is based on the notion of a "neighborhood graph" which is used in guiding an iterative improvement algorithm that produces placements which satisfy given timing constraints. An integer programming approach is being used for the third problem, because this avoids parallel long wires that are close together in the routing solution.

主要研究VLSI CAD设计的高层次综合与布局算法。复杂的、大型工业类型的设计问题的算法正在被开发。研究课题包括：1。以可测性为重要优良指标的高级综合；2 .定时驱动的epga布局算法；要考虑串扰影响的信道和开关箱路由。针对第一个问题，研究了寄存器分配和功能单元绑定对电路可测试性的影响。此时正在检查调度步骤。第二个问题的研究基于“邻域图”的概念，该概念用于指导迭代改进算法，该算法产生满足给定时间约束的位置。第三个问题使用整数规划方法，因为这避免了路由解决方案中靠近的并行长导线。