Research in Computer-Aided Design of VLSI Circuits

这项研究是关于VLSI CAD设计的高级综合和版图的算法。针对复杂的大型工业类型设计问题的算法正在开发中。研究内容包括：1.以可测试性为重要指标的高层次综合；2.基于时序驱动的EPGA布局算法；3.考虑串扰影响的通道布线和开关盒布线。对于第一个问题，正在研究寄存器分配和功能单元绑定对电路可测试性的影响。然后检查调度步骤。对第二个问题的研究基于“邻域图”的概念，它被用来指导迭代改进算法，该算法产生满足给定时间约束的布局。第三个问题使用整数规划方法，因为这避免了布线解决方案中靠近的平行长导线。

Liu The research is on algorithms for high level synthesis and layout of VLSI CAD designs. Algorithms for complex, large industrial type design problems are being developed. Research topics include: 1. high level synthesis with testability as an important goodness measure, 2. timing driven placement algorithms for EPGAs, and 3. channel and switchbox routing in which the effect of cross talk is to be taken into consideration. For the first problem, the effect of register allocation and functional unit binding on the testability of the circuit is being examined. Then the scheduling step is being examined. Research on the second problem is based on the notion of a "neighborhood graph" which is used in guiding an iterative improvement algorithm that produces placements which satisfy given timing constraints. An integer programming approach is being used for the third problem, because this avoids parallel long wires that are close together in the routing solution.