Speculative and Predicated Execution Support for Instruction-Level Parallel Processing

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Hwu Speculative execution and predicated execution are two important sources of parallelism for VLIW and superscalar processors. Speculative execution tentatively executes instructions before knowing that their execution is required. Predicated execution merges multiple possible execution paths into a single path so that the hardware can simultaneously process multiple paths. Both methods allow the compiler to extract program parallelism in the presence of conditional branches. With superscalar and VLIW designs becoming increasingly popular in the microprocessor industry, these methods have become increasingly important for future high performance microprocessors to achieve their performance goals. This project addresses three critical issues involved in incorporating speculative execution and predicated execution into future superscalar and VLIW microprocessor systems. First, the design complexity of increasing levels of architecture support for speculative execution and predicated execution are being studied. Secondly, compiler optimizers and schedulers that exploit each level of the architecture support are being developed. Thirdly, an integrated approach is being defined to coordinate speculative execution and predicated execution to best improve program execution performance. The objective is to provide architecture expertise and compiler prototypes required for the microprocessor industry to understand the cost and effectiveness of each level of hardware support.