RIA: Strategies and Methods for High Quality Delay Testing

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This research is on developing strategies and methods to generate high quality tests for all faults that might affect the performance of a circuit. In the case where a fault may affect a circuit's performance, under any timing defect, a test under the most stringent condition for which the fault is testable must be done. To this end, three topics are being investigated. First, new testability conditions are being formulated for faults that are not testable under all existing conditions, and test generation methods for such faults are being investigated. Second, methods for automatic generation of validatable, non-robust tests of the highest quality are being developed. Third, methods for generating non-robust tests with high robustness are being explored.