Test Techniques for Deep Submicron Devices

点击翻译按钮获取中文摘要

This research focuses on developing modeling, analysis and vectorgeneration techniques for some of the emerging deep submicron defects.Specifically, this project is developing techniques to model the excessivepower supply noise, the interconnect crosstalk faults and the resistiveshort and open faults as statistical delay faults. The results of themodeling process are being used to select target delay faults for testevaluation and test generation. This project further investigates vectorgeneration techniques for the selected target delay faults. The tests notonly activate and propagate the faults but also cause various worst-casenoises such that the propagation delay along the sensitized path ismaximized. Furthermore, DFT requirements and rules for eliminating orreducing the probability of having certain noise faults and for simplifyingvector generation for these faults are being explored.