Architectural Co-Synthesis for High-Performance Distributed Embedded Systems

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Embedded computing systems must be designed to meet hard, soft, performance, cost and other constraints. This research studies the synthesis of embedded systems built from multiple processors, which may be commercial or application-specific ICs connected in a network. This methodology, co-synthesis, aims to simultaneously design the hardware and software architectures of a system. Algorithms for meeting all constraints through iteration of both the hardware architecture of the distributed computing engine and the process architecture of the application software are being investigated. The model for the research is the task graph and distributed system graph. These are being extended based on simultaneous design the hardware and software, stronger assumptions about processes in the task graph, and simultaneous scheduling, allocation, and partitioning of processes during co-synthesis. Mathematical optimization methods, such as graph partitioning and network flow, are being used to generate effective design algorithms.