NYI: Aggressive Scheduling for Instructor-Level Processors

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In this project, aggressive instruction scheduling techniques for instruction-level parallel (ILP) processors are investigated. ILP processors, such as superscalar and VLIW processors, are used effectively in both general purpose and scientific computer systems. For general purpose systems, the high frequency of branch instructions creates the need for aggressive global scheduling techniques that support speculatively and conditionally executed instructions. For scientific systems, cyclic scheduling techniques such as software pipelining have been developed to aggressively schedule inner loops. The four areas that are explored in this project are: (1) Investigate issues associated with the software pipelining technique and Modulo scheduling. These include scheduling while loops, handling loops with cross- iter\-ation dependencies and removing the uniform initiation interval restriction; (2) Formalize an operation-level intermediate program representation that allows the application of well-known local scheduling techniques to achieve globally scheduled code. This approach has been successfully applied to Modulo Scheduling and is extended to acyclic scheduling; (3) Develop a task granularity adjustment methodology, similar in concept to vectorization, for software pipelining in a superscalar/VLIW based multiple processor system; and (4) Analyze the control architectures for superscalar implementations of existing processors by studying the hardware and compiler design complexities associated with scheduling multi-way branching and partial predication architectures.