Protection and Translation in Multimodel Multiprocessors: The MIP FUGU Workstation

多模型多处理器中的保护和转换：MIP FUGU 工作站

• 批准号: 9504399
• 负责人: Anant Agarwal
• 金额: $ 80万
• 依托单位: Massachusetts Institute of Technology
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 1995
• 资助国家: 美国
• 起止时间: 1995-08-15 至 1998-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9504399&HistoricalAwards=false
• 关键词: Protection; Translation; Multimodel; Multiprocessors; MIP

This project is extending the Alewife multiprocessor to explore two aspects of future scalable multiprocessors. One aspect is protection. Protection is required on accesses to hardware resources, with as little software overhead as possible. For example, when a message sender and receiver are part of the same application, they should be able to directly access network hardware. The other aspect is address translation, so that each application can have its own address space. All processors executing an application must have the same address space, however. To ensure this, memory mapping hardware is placed at each node of the multiprocessor, and must be kept coherent. The FUGU system provides three modes of interprocessor communication. Shared memory is provided by hardware synthesized messages among nodes, which maintain cache coherence. Short messages can be sent directly by performing loads and stores to I/O registers that are in each node's address space. Longer messages are managed by a DMA engine that is separate from the processor. Translation and protection for shared memory and for short messages are provided by hardware enhancements that maintain coherence in the translation lookaside buffers and ensure that messages are received only by the processes that they are addressed to. For long messages, only minimal support for address translation is provided by the hardware since the need for such translation is likely to be rare. Any needed translation will be provided by software.

这个项目扩展了Alewife多处理器，以探索未来可扩展多处理器的两个方面。一个方面是保护。在访问硬件资源时需要保护，同时尽可能减少软件开销。例如，当消息发送方和接收方是同一应用程序的一部分时，它们应该能够直接访问网络硬件。另一个方面是地址转换，这样每个应用程序都可以有自己的地址空间。但是，执行应用程序的所有处理器必须具有相同的地址空间。为了确保这一点，内存映射硬件被放置在多处理器的每个节点上，并且必须保持一致。FUGU系统提供三种处理器间通信模式。共享内存由节点间的硬件合成消息提供，保持了缓存的一致性。短消息可以通过对每个节点地址空间中的I/O寄存器执行加载和存储来直接发送。较长的消息由独立于处理器的DMA引擎管理。共享内存和短消息的翻译和保护是由硬件增强提供的，这些增强在翻译暂置缓冲区中保持一致性，并确保消息仅由它们的寻址进程接收。对于长消息，硬件只提供最低限度的地址转换支持，因为很少需要这种转换。任何需要的翻译将由软件提供。