CAREER: Improving the Access-Execute Balance in High Performance Processors

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Program behavior studies reveal that most current high performance processors spend more time computing addresses and accessing data than performing the functional operations required by application programs. This research consists of investigating issues in the design of a balanced multiple issues architecture that improves the access-execute balance, maximized the decoupling between the various functional units, exploits higher concurrency and achieves higher performance. The techniques used to alleviate access- execute imbalance include (I) executing multiple access tasks in parallel, (ii) providing architectural support for complex access primitives, and (iii) providing application- specific access primitives. Also performed will be investigations on improving concurrency between access and execute processes. Concurrency between access and execution has been exploited by queues in many decoupled access- execute architectures, but data dependent control dependencies often prohibit prefetching of data to queues. This research will investigate techniques to facilitate anticipatory loading to queues even in presence of data dependent control dependencies. The research will build on the PI's previous studies on accessexecute decoupling and other schemes to improve the performance of memory accessing. The PI is incorporating innovative techniques such as active learning, and cooperative learning into the classroom. She wants to emphasize design, design automation, and experimental aspects in her courses. As part of curriculum improvement, a new graduate course on Advanced Computer architecture and an undergraduate course and laboratory on Digital Design using FPGAs are being developed. The PI also plans to participate in outreach activities for high-school students and special programs for women and minorities. The overall objective is to stimulate efficient learning at graduate, undergraduate and pre-college levels of education. ***