Simultaneous Multireading

点击翻译按钮获取中文摘要

This is a project to develop and extend support for multithreaded computation on superscalar processors. The intention is to provide high processor utilization despite increasing memory latency. In simultaneous multithreading, multiple independent threads will issue instructions to a superscalar processor's functional units in a single cycle. The objective of this project is to fully define the low-level architecture for simultaneous multithreading, including scheduling, register architecture, pipeline design, and speculative execution. The project is developing compiler and operating systems support for multithreaded execution on the new processor architecture. A primary goal is to maximize multiple thread performance without increasing single thread latency. Most measurements are from detailed simulations, using simulators and compilers provided by industrial partners.