Code Scheduling Under Varying Parallel Resource Constraints

不同并行资源约束下的代码调度

• 批准号: 9114167
• 负责人: Susan Eggers
• 金额: $ 5万
• 依托单位: University of Washington
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 1992
• 资助国家: 美国
• 起止时间: 1992-02-01 至 1993-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9114167&HistoricalAwards=false
• 关键词: Code; Scheduling; Under; Varying; Parallel

One of the major unsolved problems in high-speed computing is designing highly parallel machines that can exploit the latent parallelism inherent in applications. Current high-speed computers do not achieve their full potential, in part because of inefficient code scheduling that leaves hardware resources underutilized. The goal of this research is to obtain better execution speedup on high- performance parallel hardware by improving code schedules. The research will develop efficient code schedulers for parallel machines with multiple instruction streams and non-blocking memory references that have long and widely varying latencies. The difficulty of scheduling for machines of this type is that, while code scheduling is a static activity, the availability and latency of the hardware that is being scheduled varies during execution time. The PI has devised four different scheduling algorithms, with varying complexity(i.e., they generate schedules with varying efficiencies) and compilation costs. They differ in whether they schedule across instructions with data dependencies and whether and in what way they take into account variances in memory latencies and multiple instruction streams. The algorithm will be evaluated when combined with the Aiken/Nicolau software pipelining algorithm and assuming a highly parallel hardware configuration. The metrics for the performance study will be code schedule size, code schedule density, execution time and hardware utilization.

高速计算中一个尚未解决的主要问题是 设计高度并行的机器， 应用程序中固有的并行性。 目前的高速计算机 无法充分发挥其潜力，部分原因是代码效率低下 调度，使硬件资源未得到充分利用。 的目标 本研究的目的是在高性能并行计算平台上获得更好的执行加速比， 通过改进代码调度来提高并行硬件性能。 该研究将开发高效的并行代码编译器 具有多指令流和非阻塞存储器的机器 具有长而广泛变化的词汇的参考文献。 的 这种类型的机器调度的困难在于，虽然代码 调度是一种静态活动， 被调度的硬件在执行时间期间变化。 的PI 设计了四种不同的调度算法， 复杂性（即，它们以不同的效率生成时间表） 和编译成本。 他们的不同之处在于， 具有数据依赖性的指令，以及它们是否以及以何种方式 考虑到存储器延迟和多个 指令流。 该算法将在合并时进行评估 使用Aiken/Nicolau软件流水线算法，并假设 高度并行硬件配置。 的指标 性能研究将是代码调度大小，代码调度密度， 执行时间和硬件利用率。