SBIR Phase I: Boundary Scan and Board-Level Built-In-Self- Test Insertion into VHDL Designs with Commercial-off-the- Shelf Components

SBIR 第一阶段：使用商用现成组件将边界扫描和板级内置自测试插入到 VHDL 设计中

• 批准号: 9661504
• 负责人: Casper Stoel
• 金额: $ 7.5万
• 依托单位: ALTERNATIVE SYSTEM CONCEPTS, INC.
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 1997
• 资助国家: 美国
• 起止时间: 1997-01-01 至 1997-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9661504&HistoricalAwards=false
• 关键词: SBIR; Phase; Boundary; Scan; Board

9661504 Stoel This Small Business Innovative Research (SBIR) Phase I project is to meet the increasing need for commercial-off-the-shelf (COTS) components in the ever shrinking time to market in the electronics industry. COTS components are readily available, less expensive, and increase efficiency of the design process, but negatively impact testability. It is proposed to develop a methodology for enhancing testability of boards and systems implemented using COTS devices, and to provide the supporting tools. The methodology will improve controllability and observabilitv in such board testing through (1) implementation of board-level JTAG boundary scan, (2) borrowing boundary scan included on some chips to test surrounding COTS components without boundary scan, and (3) integrating other test and diagnostic techniques such as board-level built-in self test (BIST) and IDDQ test using the 1149.1 standard boundary scan serial interface. Industry standards (VHDL and Boundary Scan) support interoperabilitv with major EDA frameworks. During Phase I, a prototype tool set will be developed for higher level (board, Multi-Chip Module, etc.) boundary scan and BIST insertion into VHDL designs. In Phase II, tool set features and capabilities will be expanded, and product commercialization will begin. The proposed test insertion methodology provides a solution to pressing problems faced by designers whose design requirements include high testability and use of untestable COTS components. The new tool set will lower cost and save time in the design phase through use of commercial parts without the attendant compromises in testability.

这个小型企业创新研究（SBIR）第一阶段项目是为了满足电子行业在不断缩短的上市时间中对商业现货（COTS）组件日益增长的需求。COTS组件很容易获得，更便宜，并且提高了设计过程的效率，但对可测试性产生了负面影响。建议开发一种方法来提高使用COTS设备实现的电路板和系统的可测试性，并提供支持工具。该方法将通过(1)实现板级JTAG边界扫描，(2)借用一些芯片上包含的边界扫描来测试周围的COTS组件而不进行边界扫描，以及(3)使用1149.1标准边界扫描串行接口集成其他测试和诊断技术，如板级内置自检（BIST）和IDDQ测试，从而提高板测试的可控性和可观察性。工业标准（VHDL和边界扫描）支持与主要EDA框架的互操作性。在第一阶段，将开发用于更高级别（电路板，多芯片模块等）边界扫描和BIST插入VHDL设计的原型工具集。在第二阶段，工具集的特性和功能将得到扩展，产品商业化将开始。所提出的测试插入方法为设计人员面临的紧迫问题提供了解决方案，这些设计要求包括高可测试性和使用不可测试的COTS组件。通过使用商业部件，新工具集将在设计阶段降低成本并节省时间，而不会影响可测试性。