CAREER: Using Critical Path Length as a Practical Peformance Metric

本研究的目标是研究使用关键路径长度来准确预测多个领域的性能，包括广域多线程、微处理器体系结构和高性能文件系统。对于广域多线程，策略是为分布式RAM计算模型开发保守的工作调度算法，并证明关键路径长度可以用来预测所产生的系统的性能。对于微处理器体系结构，其策略是通过将普通串行C程序编译成数据流图并测量其关键路径长度来基本了解它们的平均并行度。鉴于这种理解，可以评估硬件机制的有效性。对于高性能文件系统，策略是使用关键路径长度来衡量文件系统工作负载的平均并行度。该项目的教育部分包括教授如何使用关键路径长度方法测量和实现高性能。正在开发一门新的高级计算机体系结构课程，该课程将侧重于微处理器的性能，并将调整高级/研究生级别的操作系统课程的方向，以强调性能。最终，将开发一门关于算法并行计算的课程。*

The goal of this research is to investigate the use of critical-path length to accurately predict performance in several domains, including wide-area multithreading, microprocessor architecture, and high-performance filesystems. For wide-area multithreading, the strategy is to develop conservative work scheduling algorithms for a distributed-RAM model of computation, and to demonstrate that the critical-path length can be used to predict the performance of the resulting system. For microprocessor architecture, the strategy is to gain a fundamental understanding of the average parallelism of ordinary serial C programs by compiling them into dataflow graphs and measuring their critical-path length. Given that understanding, the effectiveness of hardware mechanisms can be evaluated. For high-performance filesystems, the strategy is to use critical-path length to measure the average parallelism of a filesystem workload. The educational component of this project includes teaching how to measure and achieve high-performance using a critical-path length methodology. A new course in advanced computer architecture is being developed which will focus on microprocessor performance, and a senior/graduate-level operating systems course will be reoriented to emphasize performance. Eventually, a course on algorithmic parallel computing will be developed.***