Memory Prefetching

早期的计算机只有在处理器请求数据后才从内存中获取数据。当内存延迟较高时，该按需获取策略也具有较高延迟。许多现代计算机在数据被请求之前就从内存中预取数据，只要预取准确、及时，就可以减少内存的延迟。这个项目是对马尔可夫预取器的初步调查，它使用马尔可夫模型来预测来自早期引用的后续内存引用。预取器充当片上和片外高速缓存之间的接口，该接口预测对存储系统的多个引用，并对它们传送到处理器的优先顺序进行排序。循环级模拟表明，马尔可夫预取器的使用减少了大约54%的内存操作导致的总体执行停滞，同时也减少了内存使用量。该项目正在扩展最初的调查，以提供对马尔可夫预取的有效性的更现实的分析，降低实现成本，并将该技术应用于多处理器系统。此外，正在研究预取的新方面，包括访问方法(读或写)的预测、处理器之间的预取以及存储器层次结构的不同级别之间的预取。主要的研究方法是循环级仿真。

Early computers fetched data from memory only after it had been requested by the processor. When memory latency is high, this demand fetch policy also has high latency. Many modern computers prefetch data from the memory before it is requested, which can reduce the latency of memory as long as the prefetching is accurate, and timely. This project is a preliminary investigation of a Markov prefetcher, which uses a Markov model to predict subsequent memory references from earlier references. The prefetcher acts as an interface between on-chip and off-chip caches that predicts multiple references to the memory system and prioritizes their delivery to the processor. Cycle-level simulations show that use of a Markov prefetcher reduces the overall execution stalls due to memory operations by about 54% while also reducing memory usage. This project is extending the initial investigation to provide more realistic analysis of the effectiveness of Markov prefetching, reduce implementation costs, and apply the technique to multiprocessor systems. In addition, new aspects of prefetching are being examined, including prediction of access methods (read or write), prefetching between processors, and prefetching between different levels of the memory hierarchy. The primary research method is cycle-level simulation.