Exploring Multiple Control Flows for ILP Processors

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Instruction-level parallel (ILP) processing has been an area of great interest in the computer architecture community and the semiconductor industry. Almost all of the processors developed since the last decade do ILP processing in a major way. Ongoing advances in ILP processing necessitate a careful examination of the amount of parallelism that exists in typical programs under various execution models. The main objective of this research is to investigate the potential of pursuing multiple control flows in ILP processors. The study starts by quantifying the effect of different control flow constraints on available parallelism. Software support for pursuing multiple control flows is then studied. Novel methods to specify control independence and data independence to the hardware are part of this study on software support. This research also studies hardware issues relevant to pursuing multiple control flows, such as tradeoffs between the number of speculative paths and performance using detailed simulation models. Preliminary simulation studies have been conducted to get an idea of the amount of parallelism available with single control flow and multiple control flows. These preliminary results indicate a factor of 2 increase in available parallelism when multiple control flows is pursued instead of a single control flow.