CAREER: Improving Compiler/Architecture Synergy

职业：提高编译器/架构的协同作用

• 批准号: 9734023
• 负责人: Gary Tyson
• 金额: $ 20万
• 依托单位: Regents of the University of Michigan - Ann Arbor
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 1998
• 资助国家: 美国
• 起止时间: 1998-03-15 至 2003-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9734023&HistoricalAwards=false
• 关键词: CAREER; Improving; Compiler; Architecture; Synergy

*** 9734023 Tyson This project explores the interaction between code transformation performed during compilation and instruction set design. Several modifications in instruction set design are under investigation, each of which attempts to improve overall processor performance by increasing the amount of compile time information transmitted to the hardware at runtime. Some modifications, such as probabilistic prefetch or branch table indexing, amount to hints that may improve performance without requiring all implementations of an architecture to use the information. Others, such as imposition of FIFO semantics on one or more register identifiers, enable compilers to schedule resources and require that all implementations comply with the scheduling. Each of the modifications will be explored using both classroom projects for graduate courses and individual research by graduate students. Simulation and other tools arising from this project will be introduced into the undergraduate curriculum. ***

*** 9734023 Tyson这个项目探索了编译期间执行的代码转换和指令集设计之间的交互。 在指令集设计的几个修改正在调查中，其中每一个试图提高整体处理器的性能，通过增加在运行时传输到硬件的编译时间信息的量。 一些修改，如概率预取或分支表索引，相当于可以提高性能的提示，而不需要架构的所有实现都使用该信息。 其他的，例如在一个或多个寄存器标识符上强加FIFO语义，使编译器能够调度资源，并要求所有实现都遵守调度。 每一个修改都将使用研究生课程的课堂项目和研究生的个人研究来探索。 模拟和其他工具，从这个项目产生的将被引入到本科课程。 ***