CISE PostDoc: Verification of Microprocessor Microarchitecture

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9805542 Launchbury, John Oregon Graduate Institute PostDoc: Verification of Microprocessor Microarchitectures Under the Post-Doctoral Research Associateship methods are being developed for verifying concurrent properties of microprocessor microarchitectures, such as liveness and sequential equivalence. Existing verification techniques are being adapted, integrated and evaluated in the context of the Hawk microarchitectural specification language. The objective of this research is to demonstrate that the use of design abstraction enables formal verification technology to be used to verify significant properties of complete microarchitectures. This work blends with parallel research on further developing the Hawk language implementation, and on using Hawk to specify realistic models of commercial microprocessors, with all their accidental complexity. The Hawk language provides abstractions that make explicit much of the information that is needed for this purpose, and the cleanliness and compactness of Hawk specifications provides powerful leverage on the verification problem. In particular, Hawk specifications avoid much of the detail of typical logic-level specifications. Further, Hawk's declarative nature provides it with great potential for formal manipulation. New, hybrid verification technology is being built by combining an appropriate temporal logic with model checking. The temporal logic is used to express the concurrent property of interest, and models are constructed automatically by abstract interpretation of Hawk specifications.