Submicron Wave-Pipelined VLSI Architecture of a Reconfigurable Router

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A critical component in the new class of computing and communication systems that facilitate smart interconnects and adaptability is the router which receives, forwards, and delivers messages. Given the reconfiguring requirements, many routing algorithms and network topologies need be supported. Thus, a flexible router is needed for these applications. A novel highly flexible router that uses a wave-pipelined architecture/organization in combination with submicron technologies is proposed. Wave-pipelining offers the potential of achieving an extremely high performance; it requires no latches between stages and its maximum clock frequencies are limited only by the path delay differences. This study is the first that involves the following three major technologies/techniques: wave-pipelining, submicron technology, and computer architecture. A comprehensive model for the architecture will be developed and verified. This model will incorporate an analysis of the system including: timing, logic signal propagation, wiring, and technology constraints. Timing constraints deal with the safe time to start computations and read results. Logic signal propagation and wiring delays are due to logic circuitry and paths between gates, respectively. Technology constraints come from the target technology. Also, a comprehensive study of the proposed router capabilities and comparison to other routers will be included in this research.