Submicron Wave-Pipelined VLSI Architecture of a Reconfigurable Router

促进智能互连和适应性的新型计算和通信系统中的一个关键组件是接收、转发和发送消息的路由器。考虑到重新配置需求，需要支持许多路由算法和网络拓扑。因此，这些应用需要灵活的路由器。提出了一种采用波管道结构/组织与亚微米技术相结合的新型高柔性路由器。波浪管道提供了实现极高性能的潜力；它不需要级之间的锁存，其最大时钟频率仅受路径延迟差异的限制。这项研究是第一个涉及以下三个主要技术的研究：波管道、亚微米技术和计算机体系结构。将开发和验证该体系结构的综合模型。该模型将包括对系统的分析，包括：时序，逻辑信号传播，布线和技术限制。时序约束处理开始计算和读取结果的安全时间。逻辑信号的传播和布线延迟分别是由于逻辑电路和门之间的路径。技术约束来自于目标技术。此外，本研究还将对所提出的路由器功能进行全面研究，并与其他路由器进行比较。

A critical component in the new class of computing and communication systems that facilitate smart interconnects and adaptability is the router which receives, forwards, and delivers messages. Given the reconfiguring requirements, many routing algorithms and network topologies need be supported. Thus, a flexible router is needed for these applications. A novel highly flexible router that uses a wave-pipelined architecture/organization in combination with submicron technologies is proposed. Wave-pipelining offers the potential of achieving an extremely high performance; it requires no latches between stages and its maximum clock frequencies are limited only by the path delay differences. This study is the first that involves the following three major technologies/techniques: wave-pipelining, submicron technology, and computer architecture. A comprehensive model for the architecture will be developed and verified. This model will incorporate an analysis of the system including: timing, logic signal propagation, wiring, and technology constraints. Timing constraints deal with the safe time to start computations and read results. Logic signal propagation and wiring delays are due to logic circuitry and paths between gates, respectively. Technology constraints come from the target technology. Also, a comprehensive study of the proposed router capabilities and comparison to other routers will be included in this research.