Exploiting Superword Level Parallelism

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Current microprocessors, which have much wider data-paths than 8 or 16 bit data-words required by multimedia workloads, are attempting to take advantage of this by offering special multimedia instructions. These extensions are a set of short SIMD or superword operations. It has been shown that short SIMD operations are well suited to exploit a fundamentally different type of parallelism than the vector parallelism associated with traditional vector supercomputers. This parallelism is denoted as Superword Level Parallelism (SLP) since parallelism comes in the form of superwords containing packed data.In this project, compiler algorithms for detection and exploitation of superword level parallelism are investigated. The compiler is extended in many directions, from dataword prediction to SLP aware register allocation, to take advantage of superword level parallelism and an extensive evaluation of these techniques is performed. Architectures that can take full advantage of SLP are also investigated in this research. Scaling the data-paths is a simple and straightforward use of the available silicon area. However, there are novel architectural features that can take full advantage of superword level parallelism.