Exploiting Superword Level Parallelism

当前的微处理器具有比多媒体工作负载所需的8或16位数据字宽得多的数据路径，正试图通过提供特殊的多媒体指令来利用这一点。这些扩展是一组短SIMD或超字操作。已经表明，短SIMD操作非常适合于利用与传统向量超级计算机相关联的向量并行性相比根本不同类型的并行性。 这种并行性被称为超字级并行性（Superword Level Parallelism，SLP），因为并行性是以包含压缩数据的超字的形式出现的。编译器扩展在许多方向，从数据字预测SLP意识到寄存器分配，利用超字级并行和这些技术进行了广泛的评估。在这项研究中，可以充分利用SLP的架构也进行了调查。 缩放数据路径是对可用硅面积的简单而直接的使用。然而，有一些新颖的架构特性可以充分利用超字级并行。

Current microprocessors, which have much wider data-paths than 8 or 16 bit data-words required by multimedia workloads, are attempting to take advantage of this by offering special multimedia instructions. These extensions are a set of short SIMD or superword operations. It has been shown that short SIMD operations are well suited to exploit a fundamentally different type of parallelism than the vector parallelism associated with traditional vector supercomputers. This parallelism is denoted as Superword Level Parallelism (SLP) since parallelism comes in the form of superwords containing packed data.In this project, compiler algorithms for detection and exploitation of superword level parallelism are investigated. The compiler is extended in many directions, from dataword prediction to SLP aware register allocation, to take advantage of superword level parallelism and an extensive evaluation of these techniques is performed. Architectures that can take full advantage of SLP are also investigated in this research. Scaling the data-paths is a simple and straightforward use of the available silicon area. However, there are novel architectural features that can take full advantage of superword level parallelism.