Technology for 24-GHz Wireless Networks

24 GHz 无线网络技术

• 批准号: 0083220
• 负责人: Ali Hajimiri
• 金额: $ 28.01万
• 依托单位: California Institute of Technology
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2000
• 资助国家: 美国
• 起止时间: 2000-10-01 至 2003-09-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0083220&HistoricalAwards=false
• 关键词: Technology; 24; GHz; Wireless; Networks

0083220HajimiriMost of the recent work in the area of wireless networks has been focused on systems operating at 2.4 and 5 GHz. The bandwidth available at these frequencies limits the maximum data rates for these networks. Very little has been done to use frequencies at or above 20 GHz for wireless networks. The major advantages of higher frequencies are higher available bandwidths, smaller antenna sizes and possibility of using phased array structures for directionality and gain boosting. The major impediment to operation at these frequencies is the large hardware cost, which originates from the large amount of circuitry that has to be done in gallium-arsenide or other III-V semiconductors.An alternative approach using a large silicon integrated circuit core and a small gallium-arsenide front-end is proposed to remedy this problem. The proposed approach uses an array of resonant microstrip patches etched on a 5-cm square printed circuit board to receive and transmit signals. The antenna system can provide a gain of 20 dB, and this great directionality is available for both transmitting and receiving. The array can scan in azimuth to find, and communicate to other units on the network, while rejecting undesired interference cause by other users. The system has a gallium-arsenide monolithic microwave integrated circuit (MMIC) that only consists of a low noise amplifier (LNA) for the receive path and a power amplifier (PA) on the transmit side. Due to the high cost of gallium arsenide components, every effort is taken to minimize the size of the gallium-arsenide circuitry.Silicon integrated circuit is at the heart of the system and is the most critical part of it. It contains the first down- and up-conversion blocks, i.e., the fully integrated frequency synthesizer operating at 21.6-GHz and two mixers down- and up-converting the signal from and to 24 GHz from a 2.45-GHz intermediate frequency (IF). This choice of IF frequency is not arbitrary and is to allow for bypassing the front-end circuitry and using a lower-frequency resonance of the array to effectively act as a single patch antenna receiving at 2.45GHz ISM band for finding other users and low bit rate data transmission in so-called sniffing mode.The fully-integrated 21.6-GHz silicon frequency synthesizer is based on using distributed voltage controlled oscillators (DVCO), which make it possible to use transistors close or even beyond their cut-off frequency, fT. These DVCOs produce a reasonable output power with good phase noise performance and large tuning range, using a novel tuning technique, known as delay-balance, current-steering tuning. A super-harmonic injection-locked frequency dividers can be used as the prescaler to divide the output frequency to lower frequencies that can be handled by digital dynamically-loaded frequency dividers to further divide to reference oscillator frequency to maintain phase lock. To demonstrate the feasibility of this approach, a 0.35-mm CMOS DVCO operating at 10 GHz with 12% tuning range and a phase noise of -104dBc/Hz at 1-MHz offset from the carrier is designed and tested. Also two silicon bipolar DVCOs operating at 12 GHz and 17 GHz are demonstrated, further verifying the feasibility of such systems.A complete analysis of MOS switching mixer makes it possible to exploit the higher bandwidth of the MOS transistor when used as switches and not gain devices. This approach which is based on stochastic differential equations with cyclostationary sources is used to optimize silicon up- and down-conversion mixers' performance at 24 GHz. It is shown that high performance circuitry for the first IF/sniff mode RF can be implemented in silicon, making it possible to integrate the complete back-end of the transceiver.

[00:83220 . hajimiri]最近无线网络领域的大部分工作都集中在2.4 GHz和5ghz的系统上。在这些频率上可用的带宽限制了这些网络的最大数据速率。在无线网络中使用20千兆赫以上的频率方面做得很少。更高频率的主要优点是更高的可用带宽，更小的天线尺寸以及使用相控阵结构进行方向性和增益提升的可能性。在这些频率下运行的主要障碍是巨大的硬件成本，这源于必须在砷化镓或其他III-V半导体中完成大量电路。提出了一种使用大硅集成电路核心和小砷化镓前端的替代方法来解决这个问题。所提出的方法使用在5厘米见方的印刷电路板上蚀刻的谐振微带贴片阵列来接收和发送信号。天线系统可以提供20 dB的增益，并且这种良好的方向性可用于发射和接收。该阵列可以进行方位角扫描查找，并与网络上的其他单元通信，同时拒绝其他用户造成的不希望的干扰。该系统采用砷化镓单片微波集成电路（MMIC），仅由用于接收路径的低噪声放大器（LNA）和用于发射侧的功率放大器（PA）组成。由于砷化镓元件的高成本，所有的努力都是为了最小化砷化镓电路的尺寸。硅集成电路是系统的核心，是系统中最关键的部分。它包含第一个下行和上行转换模块，即工作在21.6 GHz的完全集成频率合成器和两个下行和上行的混频器，从2.45 GHz中频（IF）将信号从21.6 GHz转换为24 GHz。这种中频频率的选择不是任意的，并且允许绕过前端电路并使用阵列的低频共振有效地充当单个贴片天线接收2.45GHz ISM频段，以查找其他用户和所谓嗅探模式下的低比特率数据传输。完全集成的21.6 ghz硅频率合成器基于分布式电压控制振荡器（DVCO），这使得使用接近甚至超过其截止频率fT的晶体管成为可能。这些DVCO使用一种新的调谐技术，即延迟平衡，电流转向调谐，产生合理的输出功率，具有良好的相位噪声性能和大的调谐范围。超谐波注入锁定分频器可作为预分频器，将输出频率分频到较低的频率，这些频率可由数字动态负载分频器处理，进一步分频到参考振荡器频率以保持锁相。为了证明该方法的可行性，设计并测试了一个0.35 mm CMOS DVCO，工作频率为10 GHz，调谐范围为12%，相位噪声为-104dBc/Hz，偏移频率为1 mhz。此外，还演示了两个工作在12 GHz和17 GHz的硅双极dvco，进一步验证了该系统的可行性。对MOS开关混频器进行完整的分析，可以充分利用MOS晶体管作为开关器件而非增益器件的更高带宽。该方法基于随机微分方程和循环平稳源，用于优化24ghz硅上下转换混频器的性能。结果表明，第一个中频/嗅探模式射频的高性能电路可以在硅中实现，从而可以集成收发器的完整后端。