Circuit Design and CAD for System Applications of Silicon-Based Quantum-Effect Devices

硅基量子效应器件系统应用的电路设计和CAD

• 批准号: 0114971
• 负责人: Pinaki Mazumder
• 金额: $ 21万
• 依托单位: Regents of the University of Michigan - Ann Arbor
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2001
• 资助国家: 美国
• 起止时间: 2001-09-01 至 2006-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0114971&HistoricalAwards=false
• 关键词: Circuit; Design; CAD; System; Applications

The Semiconductor Industries Association (SIA) projects that the accrued benefits of the device shrinking era will continue for another decade or so, until feature sizes reach their ultimate limit of around 70 nm. Beyond then, during the post-shrinking era, newer electronic, photonic and molecular technologies must emerge to push the demands for higher system integration on a chip (SOC) and lower energy dissipation. At the present time, substantial research initia-tive focused on quantum-effect devices has demonstrated that these devices offer the best solution for next generation high-performance integrated circuits. Simulation results have shown that circuits designed using resonant-tunneling diodes (RTDs) and complementary metal-oxide-semiconductor (CMOS) transistors can offer an order of magnitude improvement in area-power-delay performance over conventional CMOS. These circuits alleviate the performance saturation that will limit conventional technologies due to diminishing returns from device- and feature-size scaling. While RTDs have been demonstrated for niche small-scale, high-speed ( 40 GHz) circuit applications using III-V process technology, no system-level designs have been fabricated that use RTD-based circuit design. The disadvantage of III-V technology is higher power dissipation and very low integration levels as compared to CMOS. However, the unique negative differential-resistance (NDR) characteristics of RTDs coupled with their high tunneling speeds lead to very compact and fast circuit topologies. Thus it is very attractive to envision these compact, high-functionality circuits implemented in a technology such as CMOS that offers low power dissipation and very large integration lev-els. Also, while transport properties of quantum-effect devices are substantially different from conventional devices, their fabrication and processing framework can be considered an extension of the current state-of-the-art, rather than a radical departure. This makes it possible to envision a synergism between conventional and quantum-effect circuits that will bridge the transition to giga-scale integration and beyond.Quantum electronic devices such as double-barrier resonant tunneling diodes and transistors offer the promise of increased speed and circuit compaction. However, the folded 1-V or negative differential resistance (NDR) charac-teristic of these devices implies that conventional circuit design techniques are not adequate to tackle the problem of optimal circuit design using these devices. Preliminary work, using ad-hoc circuit design techniques, has demonstrated the possibility of building innovative, ultrafast and compact circuits using resonant tunneling devices. This proposal seeks to develop the theory of circuit design using quantum-effect devices, to design accurate and fast circuit simu-lation models and algorithms for the quantum-effect devices, and to study system-level issues in the design of large computational, communication system, and signal processing circuits using quantum-effect devices.The proposed work is divided into three tasks. In the first task, circuit simulation models and algorithms will be developed for quantum-effect resonant tunneling devices. These models, based on values obtained from quantum simulation, and other physics-based models, will be enhanced with algorithms to ensure the convergence of table-driven simulation. In the second task, essential circuit theory for quantum-effect circuits will be developed. This will include stability analysis and optimization techniques for bistable and combinational logic circuits using quantum-effect devices. In the third task, the basic circuit techniques developed in the second task will be applied to the design of nanopipelined and multiple-valued logic systems using quantum-effect devices. The simulation work done in the first task will be used for performance projection of system-level application of quantum-effect devices. Circuit fabrication for QMOS prototypes will be carried out to demonstrate the advantages of the new technology.

半导体工业协会（SIA）预计，器件缩小时代的累积效益将持续10年左右，直到特征尺寸达到70纳米左右的最终极限。除此之外，在后收缩时代，必须出现更新的电子，光子和分子技术，以推动对更高系统集成芯片（SOC）和更低能耗的需求。目前，对量子效应器件的大量研究表明，这些器件为下一代高性能集成电路提供了最佳解决方案。仿真结果表明，采用谐振隧道二极管（rtd）和互补金属氧化物半导体（CMOS）晶体管设计的电路可以提供一个数量级的面积功率延迟性能比传统的CMOS。这些电路缓解了性能饱和，这将限制传统技术，因为设备和功能尺寸缩放的回报递减。虽然rtd已经被证明适用于小型、高速（40 GHz）电路应用，但目前还没有采用基于rtd的电路设计的系统级设计。与CMOS相比，III-V技术的缺点是更高的功耗和非常低的集成水平。然而，rtd独特的负差分电阻（NDR）特性加上它们的高隧道速度导致非常紧凑和快速的电路拓扑结构。因此，设想这些紧凑、高功能的电路在CMOS等技术中实现是非常有吸引力的，这些技术提供了低功耗和非常大的集成水平。此外，虽然量子效应器件的输运特性与传统器件有很大不同，但它们的制造和加工框架可以被认为是对当前最先进技术的延伸，而不是彻底的背离。这使得设想传统电路和量子效应电路之间的协同作用成为可能，这将架起过渡到千兆级集成和超越的桥梁。量子电子器件，如双势垒共振隧道二极管和晶体管，提供了提高速度和电路压缩的希望。然而，这些器件的折叠1-V或负差分电阻（NDR）特性意味着传统的电路设计技术不足以解决使用这些器件的最佳电路设计问题。初步工作，使用特设电路设计技术，已经证明了使用谐振隧道器件构建创新，超快和紧凑电路的可能性。本提案旨在发展利用量子效应器件的电路设计理论，为量子效应器件设计准确、快速的电路仿真模型和算法，并研究利用量子效应器件设计大型计算、通信系统和信号处理电路中的系统级问题。建议的工作分为三个任务。在第一项任务中，将开发量子效应谐振隧道器件的电路仿真模型和算法。这些基于量子模拟和其他基于物理的模型的模型将通过算法进行增强，以确保表驱动模拟的收敛性。在第二项任务中，将发展量子效应电路的基本电路理论。这将包括稳定性分析和优化技术双稳态和组合逻辑电路使用量子效应器件。在第三项任务中，第二项任务中开发的基本电路技术将应用于使用量子效应器件设计纳米管道和多值逻辑系统。在第一个任务中所做的模拟工作将用于量子效应器件系统级应用的性能预测。将进行QMOS原型的电路制造，以展示新技术的优势。