Circuit Design and CAD for System Applications of Silicon-Based Quantum-Effect Devices

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The Semiconductor Industries Association (SIA) projects that the accrued benefits of the device shrinking era will continue for another decade or so, until feature sizes reach their ultimate limit of around 70 nm. Beyond then, during the post-shrinking era, newer electronic, photonic and molecular technologies must emerge to push the demands for higher system integration on a chip (SOC) and lower energy dissipation. At the present time, substantial research initia-tive focused on quantum-effect devices has demonstrated that these devices offer the best solution for next generation high-performance integrated circuits. Simulation results have shown that circuits designed using resonant-tunneling diodes (RTDs) and complementary metal-oxide-semiconductor (CMOS) transistors can offer an order of magnitude improvement in area-power-delay performance over conventional CMOS. These circuits alleviate the performance saturation that will limit conventional technologies due to diminishing returns from device- and feature-size scaling. While RTDs have been demonstrated for niche small-scale, high-speed ( 40 GHz) circuit applications using III-V process technology, no system-level designs have been fabricated that use RTD-based circuit design. The disadvantage of III-V technology is higher power dissipation and very low integration levels as compared to CMOS. However, the unique negative differential-resistance (NDR) characteristics of RTDs coupled with their high tunneling speeds lead to very compact and fast circuit topologies. Thus it is very attractive to envision these compact, high-functionality circuits implemented in a technology such as CMOS that offers low power dissipation and very large integration lev-els. Also, while transport properties of quantum-effect devices are substantially different from conventional devices, their fabrication and processing framework can be considered an extension of the current state-of-the-art, rather than a radical departure. This makes it possible to envision a synergism between conventional and quantum-effect circuits that will bridge the transition to giga-scale integration and beyond.Quantum electronic devices such as double-barrier resonant tunneling diodes and transistors offer the promise of increased speed and circuit compaction. However, the folded 1-V or negative differential resistance (NDR) charac-teristic of these devices implies that conventional circuit design techniques are not adequate to tackle the problem of optimal circuit design using these devices. Preliminary work, using ad-hoc circuit design techniques, has demonstrated the possibility of building innovative, ultrafast and compact circuits using resonant tunneling devices. This proposal seeks to develop the theory of circuit design using quantum-effect devices, to design accurate and fast circuit simu-lation models and algorithms for the quantum-effect devices, and to study system-level issues in the design of large computational, communication system, and signal processing circuits using quantum-effect devices.The proposed work is divided into three tasks. In the first task, circuit simulation models and algorithms will be developed for quantum-effect resonant tunneling devices. These models, based on values obtained from quantum simulation, and other physics-based models, will be enhanced with algorithms to ensure the convergence of table-driven simulation. In the second task, essential circuit theory for quantum-effect circuits will be developed. This will include stability analysis and optimization techniques for bistable and combinational logic circuits using quantum-effect devices. In the third task, the basic circuit techniques developed in the second task will be applied to the design of nanopipelined and multiple-valued logic systems using quantum-effect devices. The simulation work done in the first task will be used for performance projection of system-level application of quantum-effect devices. Circuit fabrication for QMOS prototypes will be carried out to demonstrate the advantages of the new technology.