Research for Mixed Signal Electronic Technologies: A Joint Initiative Between NSF and SRC: CAD Tool for High-Level Design Automation of Integrated Mixed-Signal Microsystems

混合信号电子技术研究:NSF 和 SRC 的联合倡议:集成混合信号微系统高级设计自动化的 CAD 工具

基本信息

  • 批准号:
    0119778
  • 负责人:
  • 金额:
    $ 15万
  • 依托单位:
  • 依托单位国家:
    美国
  • 项目类别:
    Continuing Grant
  • 财政年份:
    2001
  • 资助国家:
    美国
  • 起止时间:
    2001-08-01 至 2005-07-31
  • 项目状态:
    已结题

项目摘要

The process for designing an integrated circuit (IC) system-on-a-chip (SoC) shares many similarities with the hardware design of a system on a board or on several boards. The hardware system designer knows the characteristics of the set of system input signals that are to be processed, and the characteristics of the set of system output signals. There are usually several signal processing architectures that can accomplish the goal and the designer must evaluate the tradeoffs that are inherent in the various designs. Board-level hardware system designers have to use available standard commercial components for the most part to create the system of desired functionality. Sometimes requirements allow for the creation of custom ICs, and occasionally a few transistors and discrete components are used to provide proper interfaces among chips. Designers evaluate the potential that various components have for meeting overall system performance requirements based upon the components' terminal characteristics. From the designers' skill and insight, an architecture is selected, the hardware realization breadboarded, and evaluated. In the process of designing an SoC IC, the terminal characteristics of the SoC inputs and outputs must be known. Often, proven board-level hardware realizations of the function are referred to as possible architectures for the SoC. These proven board-level architectures are defined in terms of the interconnection of the group of commercial products that provide various signal processing sub-functions. The SoC architecture can also be defined in terms of these sub-function modules. Partitioning the SoC into blocks that correspond to the sub-functions successfully used in board-level designs is usually convenient because the characteristics of the sub-functions' interconnecting signals are well understood. The performance required of each of the SoC sub-functions must be inferred from the performance specifications of the overall SoC. However, the SoC IC designers do not have available these sub-functions as performance-characterized cells laid out in the target fabrication technology. The SoC IC design team usually has to create each of the sub-function blocks as a custom IC cell. The transistor-level topologies of analog and digital functional blocks are then identified and evaluated.Existing CAD tools are capable of sizing MOS transistors of circuits with modest complexity to customize the circuit to meet design specifications through performance function minimization. One SoC IC design problem is to select the sub-function performance requirements in such a way as to optimize the overall SoC performance. It is possible to find these optimized sub-functions' performance requirements using the overall SoC performance specifications and performance function optimization techniques. A new CAD tool that can optimize the SoC sub-function performances based upon the overall SoC performance requirements will be created. The resultant optimized sub-function performance requirements can then become the inputs to other existing design optimization CAD tools that perform subsequent more-detailed design automation steps to create the transistor-level circuit realizations.Integrated micro-systems, systems-on-a-chip, will be very complex combinations of analog, digital, mixed-signal, photonic, and MEMS signal processing functions. The analysis, design, and design verification of such a system is incredibly complicated, and will require the use of many very sophisticated CAD tools. At the present time and in the near future, it is unrealistic to expect a single integrated suite of CAD design tools to be able to provide all of the capabilities needed to design, layout, and verify the functionality of an SoC that includes extensive digital functionality, and analog, mixed-signal, photonic, and MEMS signal processing sub-systems. Research will be undertaken on an integrated micro-system design automation tool that will optimize the performance of a complex mixed-signal signal-processing SoC entirely at the conceptual level. Research in behavioral modeling, high-level system performance specification, and performance optimization by objective function minimization will be undertaken to support this effort. To facilitate this overall goal, flexible, accurate, computationally efficient, technology-independent, implementation-independent, high-conceptual-level behavioral models that reflect all important limiting effects of the function that could influence SoC performance are required that represent the many diverse possible actions that can be taken by the various subsystems of an SoC. Analog, digital, mixed-signal, photonic, and MEMS devices that may be included on an SoC will considered in this research.One deliverable is a fully documented design environment that supports the capture of an SoC functional description as an interconnection of sub-functions defined in a library of high-conceptual-level behavioral models, and capture of the SoC performance requirements and specifications. This design environment will also facilitate highly efficient system simulation using the behavioral models and an analysis engine. Another deliverable is a fully documented library of technology-independent, implementation-independent, high-conceptual-level, behavioral models. All results will be available for use by others on a project web site. Libraries of behavioral models and behavioral modeling tools will be organized into a designer "toolbox". This CAD tool will be created in standard programming languages and will be easily disseminated.
设计集成电路(IC)片上系统(SoC)的过程与在一块板上或几个板上设计系统的硬件设计有许多相似之处。硬件系统设计者知道要处理的一组系统输入信号的特性,以及一组系统输出信号的特性。通常有几种信号处理架构可以实现目标,设计师必须评估各种设计中固有的权衡。板级硬件系统设计人员必须在大多数情况下使用可用的标准商用组件来创建所需功能的系统。有时需求允许创建定制ic,偶尔使用几个晶体管和分立组件来提供芯片之间的适当接口。设计人员根据组件的终端特性评估各种组件满足整体系统性能要求的潜力。根据设计人员的技能和洞察力,选择了一种架构,硬件实现板,并进行了评估。在SoC的设计过程中,必须知道SoC输入和输出的终端特性。通常,经过验证的板级硬件实现功能被称为SoC的可能架构。这些经过验证的板级架构是根据提供各种信号处理子功能的商业产品组的互连来定义的。SoC架构也可以根据这些子功能模块来定义。将SoC划分为与板级设计中成功使用的子功能相对应的块通常很方便,因为子功能互连信号的特征很容易理解。每个SoC子功能所需的性能必须从整体SoC的性能规格中推断出来。然而,SoC IC设计者并没有将这些子功能作为目标制造技术中布置的性能表征单元。SoC IC设计团队通常必须创建每个子功能块作为定制IC单元。然后对模拟和数字功能块的晶体管级拓扑进行识别和评估。现有的CAD工具能够对具有中等复杂性的电路的MOS晶体管进行尺寸调整,从而通过性能功能最小化来定制电路以满足设计规范。SoC IC设计的一个问题是选择子功能性能需求,以优化SoC的整体性能。使用整体SoC性能规范和性能功能优化技术可以找到这些优化的子功能的性能需求。将创建一个新的CAD工具,可以根据SoC的整体性能要求优化SoC子功能的性能。最终优化的子功能性能要求可以成为其他现有设计优化CAD工具的输入,这些工具执行后续更详细的设计自动化步骤,以创建晶体管级电路实现。集成微系统,即片上系统,将是模拟、数字、混合信号、光子和MEMS信号处理功能的非常复杂的组合。这样一个系统的分析、设计和设计验证是非常复杂的,并且需要使用许多非常复杂的CAD工具。在目前和不久的将来,期望一套集成的CAD设计工具能够提供设计、布局和验证SoC功能所需的所有功能是不现实的,SoC包括广泛的数字功能、模拟、混合信号、光子和MEMS信号处理子系统。将研究集成微系统设计自动化工具,该工具将在概念层面完全优化复杂混合信号处理SoC的性能。行为建模、高级系统性能规范和目标函数最小化的性能优化方面的研究将支持这一努力。为了实现这一总体目标,需要灵活、准确、计算高效、技术独立、实现独立、高概念级的行为模型,这些模型反映了可能影响SoC性能的功能的所有重要限制效应,这些模型代表了SoC的各个子系统可以采取的许多不同的可能行动。模拟,数字,混合信号,光子和MEMS器件可能包括在SoC将在本研究中考虑。一个可交付的成果是一个完全文档化的设计环境,它支持捕获SoC功能描述,作为在高概念级行为模型库中定义的子功能的互连,并捕获SoC性能需求和规范。该设计环境还将促进使用行为模型和分析引擎的高效系统仿真。另一个可交付成果是一个完全文档化的库,其中包含独立于技术、独立于实现、高概念级别的行为模型。所有的结果将提供给项目网站上的其他人使用。行为模型库和行为建模工具将被组织成一个设计师“工具箱”。这种计算机辅助设计工具将以标准的程序设计语言编写,并易于传播。

项目成果

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Karl Current其他文献

Karl Current的其他文献

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{{ truncateString('Karl Current', 18)}}的其他基金

Modeling and Characterization of Integrated Multiple Valued Logic Circuits
集成多值逻辑电路的建模和表征
  • 批准号:
    7902980
  • 财政年份:
    1979
  • 资助金额:
    $ 15万
  • 项目类别:
    Standard Grant
Travel to Attend: 9th International Symposium on Multiple Valued Logic; Bath, England; May 29-31, 1979
出差参加:第九届多值逻辑国际研讨会;
  • 批准号:
    7910769
  • 财政年份:
    1979
  • 资助金额:
    $ 15万
  • 项目类别:
    Standard Grant

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  • 批准号:
    82302303
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    2023
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    30 万元
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    青年科学基金项目

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