SBIR Phase I: Next Generation Binary Decision Diagrams (BDD)-Based Logic Optimization System

点击翻译按钮获取中文摘要

This Small Business Innovation Research Phase I project addresses the need to synthesize very large silicon chips designs in very short time. Currently available commercial synthesis tools are based on the methodology, data structures, and algorithms that are predominantly algebraic (as opposed to more efficient Boolean methods), and are characterized by slow run time and inadequate design quality. This SBIR project is devoted to the development of efficient algorithms and techniques for logic synthesis based on modern BDD data structures. At the heart of the algorithms is a novel BDD decomposition theory, recently developed by company researchers. The resulting commercial product is a software solution for very fast, high-performance logic synthesis; as indicated by initial experiments it will be at least an order of magnitude faster than software tools available on the market today. The main version of the product is a core engine for logic synthesis used in several classes of applications: ASICs, microprocessors, and FPGAs. Another version of the tool will target formal verification, which also relies on fast logic optimization. The logic optimization engine can be plugged into any existing synthesis flow utilized by customers and offered by the existing EDA software vendors The SBIR Phase I project will stimulate research in design automation and inject much needed innovation in the EDA industry. This work will culminate in the development of a next generation, high-performance logic synthesis system that will have a significant commercial impact on the EDA tools market. This activity will also have important educational impact. It will educate a new generation of design engineers and students by exposing them to new design methodologies and innovations pioneered by this project.