Compiling for and Designing Next Generation Memory Systems

点击翻译按钮获取中文摘要

The most pressing obstacle to achieving high computer performance isthat CPUs compute faster than the computer can move data to the CPU. Because programs usually have regular and repetitive accesses, currentcomputers cache recently accessed data in a hierarchy of fast, flatinclusive memories to improve performance. Technology trends aremaking the data delivery problem much worse and will force changes toto memory design such as partitioned cache levels. We propose a richsoftware/hardware interface to manage next generation caches. Wepropose new compiler algorithms to translate programs to performbetter on this new hardware, and new hardware designs that enable thecompiler to inform the hardware of current and future data accesspatterns. These new techniques will go well beyond the currentminimalist load and store architecture/compiler interface to achievehigh performance. The result will enable end users of computer systemsto solve their problems more quickly and easily. The research willhave broad impact on the design and implementation of software andhardware cache architectures. It will add new and enhanced tools tothe compiler, tool, and simulation national research infrastructure.This work will also train graduate students in advanced research.